mirror of
https://github.com/citra-mirror/citra.git
synced 2024-08-19 18:13:21 +02:00
arm_dyncom_interpreter: Simplify assignment in SMLAW
Also a side-benefit of not having implementation-defined behavior.
This commit is contained in:
parent
078bf29d1d
commit
23dbbb786a
@ -5695,7 +5695,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
|
|||||||
const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF);
|
const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF);
|
||||||
const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16);
|
const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16);
|
||||||
|
|
||||||
RD = (result & (0xFFFFFFFFFFFFFFFFLL >> 15)) >> 16;
|
RD = BITS(result, 16, 47);
|
||||||
|
|
||||||
if ((result >> 16) != (s32)RD)
|
if ((result >> 16) != (s32)RD)
|
||||||
cpu->Cpsr |= (1 << 27);
|
cpu->Cpsr |= (1 << 27);
|
||||||
|
Loading…
Reference in New Issue
Block a user