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https://github.com/citra-mirror/citra.git
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Merge pull request #2335 from yuriks/shader-refactor
Misc. Shader refactors
This commit is contained in:
commit
2ca548bbe5
@ -39,6 +39,7 @@ set(HEADERS
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rasterizer.h
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rasterizer.h
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rasterizer_interface.h
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rasterizer_interface.h
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renderer_base.h
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renderer_base.h
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shader/debug_data.h
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shader/shader.h
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shader/shader.h
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shader/shader_interpreter.h
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shader/shader_interpreter.h
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swrasterizer.h
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swrasterizer.h
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@ -138,7 +138,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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if (immediate_attribute_id >= regs.vs.num_input_attributes + 1) {
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if (immediate_attribute_id >= regs.vs.num_input_attributes + 1) {
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immediate_attribute_id = 0;
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immediate_attribute_id = 0;
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Shader::UnitState<false> shader_unit;
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Shader::UnitState shader_unit;
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g_state.vs.Setup();
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g_state.vs.Setup();
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// Send to vertex shader
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// Send to vertex shader
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@ -237,7 +237,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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unsigned int vertex_cache_pos = 0;
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unsigned int vertex_cache_pos = 0;
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vertex_cache_ids.fill(-1);
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vertex_cache_ids.fill(-1);
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Shader::UnitState<false> shader_unit;
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Shader::UnitState shader_unit;
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g_state.vs.Setup();
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g_state.vs.Setup();
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for (unsigned int index = 0; index < regs.num_vertices; ++index) {
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for (unsigned int index = 0; index < regs.num_vertices; ++index) {
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186
src/video_core/shader/debug_data.h
Normal file
186
src/video_core/shader/debug_data.h
Normal file
@ -0,0 +1,186 @@
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// Copyright 2016 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <vector>
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#include "common/common_types.h"
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#include "common/vector_math.h"
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#include "video_core/pica_types.h"
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namespace Pica {
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namespace Shader {
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/// Helper structure used to keep track of data useful for inspection of shader emulation
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template <bool full_debugging>
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struct DebugData;
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template <>
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struct DebugData<false> {
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// TODO: Hide these behind and interface and move them to DebugData<true>
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u32 max_offset = 0; ///< maximum program counter ever reached
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u32 max_opdesc_id = 0; ///< maximum swizzle pattern index ever used
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};
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template <>
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struct DebugData<true> {
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/// Records store the input and output operands of a particular instruction.
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struct Record {
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enum Type {
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// Floating point arithmetic operands
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SRC1 = 0x1,
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SRC2 = 0x2,
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SRC3 = 0x4,
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// Initial and final output operand value
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DEST_IN = 0x8,
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DEST_OUT = 0x10,
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// Current and next instruction offset (in words)
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CUR_INSTR = 0x20,
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NEXT_INSTR = 0x40,
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// Output address register value
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ADDR_REG_OUT = 0x80,
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// Result of a comparison instruction
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CMP_RESULT = 0x100,
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// Input values for conditional flow control instructions
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COND_BOOL_IN = 0x200,
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COND_CMP_IN = 0x400,
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// Input values for a loop
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LOOP_INT_IN = 0x800,
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};
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Math::Vec4<float24> src1;
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Math::Vec4<float24> src2;
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Math::Vec4<float24> src3;
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Math::Vec4<float24> dest_in;
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Math::Vec4<float24> dest_out;
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s32 address_registers[2];
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bool conditional_code[2];
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bool cond_bool;
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bool cond_cmp[2];
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Math::Vec4<u8> loop_int;
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u32 instruction_offset;
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u32 next_instruction;
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/// set of enabled fields (as a combination of Type flags)
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unsigned mask = 0;
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};
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u32 max_offset = 0; ///< maximum program counter ever reached
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u32 max_opdesc_id = 0; ///< maximum swizzle pattern index ever used
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/// List of records for each executed shader instruction
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std::vector<DebugData<true>::Record> records;
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};
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/// Type alias for better readability
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using DebugDataRecord = DebugData<true>::Record;
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/// Helper function to set a DebugData<true>::Record field based on the template enum parameter.
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template <DebugDataRecord::Type type, typename ValueType>
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inline void SetField(DebugDataRecord& record, ValueType value);
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template <>
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inline void SetField<DebugDataRecord::SRC1>(DebugDataRecord& record, float24* value) {
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record.src1.x = value[0];
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record.src1.y = value[1];
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record.src1.z = value[2];
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record.src1.w = value[3];
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}
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template <>
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inline void SetField<DebugDataRecord::SRC2>(DebugDataRecord& record, float24* value) {
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record.src2.x = value[0];
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record.src2.y = value[1];
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record.src2.z = value[2];
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record.src2.w = value[3];
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}
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template <>
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inline void SetField<DebugDataRecord::SRC3>(DebugDataRecord& record, float24* value) {
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record.src3.x = value[0];
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record.src3.y = value[1];
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record.src3.z = value[2];
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record.src3.w = value[3];
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}
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template <>
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inline void SetField<DebugDataRecord::DEST_IN>(DebugDataRecord& record, float24* value) {
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record.dest_in.x = value[0];
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record.dest_in.y = value[1];
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record.dest_in.z = value[2];
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record.dest_in.w = value[3];
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}
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template <>
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inline void SetField<DebugDataRecord::DEST_OUT>(DebugDataRecord& record, float24* value) {
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record.dest_out.x = value[0];
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record.dest_out.y = value[1];
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record.dest_out.z = value[2];
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record.dest_out.w = value[3];
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}
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template <>
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inline void SetField<DebugDataRecord::ADDR_REG_OUT>(DebugDataRecord& record, s32* value) {
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record.address_registers[0] = value[0];
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record.address_registers[1] = value[1];
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}
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template <>
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inline void SetField<DebugDataRecord::CMP_RESULT>(DebugDataRecord& record, bool* value) {
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record.conditional_code[0] = value[0];
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record.conditional_code[1] = value[1];
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}
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template <>
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inline void SetField<DebugDataRecord::COND_BOOL_IN>(DebugDataRecord& record, bool value) {
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record.cond_bool = value;
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}
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template <>
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inline void SetField<DebugDataRecord::COND_CMP_IN>(DebugDataRecord& record, bool* value) {
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record.cond_cmp[0] = value[0];
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record.cond_cmp[1] = value[1];
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}
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template <>
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inline void SetField<DebugDataRecord::LOOP_INT_IN>(DebugDataRecord& record, Math::Vec4<u8> value) {
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record.loop_int = value;
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}
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template <>
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inline void SetField<DebugDataRecord::CUR_INSTR>(DebugDataRecord& record, u32 value) {
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record.instruction_offset = value;
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}
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template <>
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inline void SetField<DebugDataRecord::NEXT_INSTR>(DebugDataRecord& record, u32 value) {
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record.next_instruction = value;
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}
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/// Helper function to set debug information on the current shader iteration.
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template <DebugDataRecord::Type type, typename ValueType>
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inline void Record(DebugData<false>& debug_data, u32 offset, ValueType value) {
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// Debugging disabled => nothing to do
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}
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template <DebugDataRecord::Type type, typename ValueType>
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inline void Record(DebugData<true>& debug_data, u32 offset, ValueType value) {
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if (offset >= debug_data.records.size())
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debug_data.records.resize(offset + 1);
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SetField<type, ValueType>(debug_data.records[offset], value);
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debug_data.records[offset].mask |= type;
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}
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} // namespace Shader
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} // namespace Pica
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@ -109,15 +109,12 @@ void ShaderSetup::Setup() {
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MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
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MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
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void ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num_attributes) {
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void ShaderSetup::Run(UnitState& state, const InputVertex& input, int num_attributes) {
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auto& config = g_state.regs.vs;
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auto& config = g_state.regs.vs;
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auto& setup = g_state.vs;
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auto& setup = g_state.vs;
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MICROPROFILE_SCOPE(GPU_Shader);
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MICROPROFILE_SCOPE(GPU_Shader);
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup input register table
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// Setup input register table
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const auto& attribute_register_map = config.input_register_map;
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const auto& attribute_register_map = config.input_register_map;
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@ -128,22 +125,23 @@ void ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num
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state.conditional_code[1] = false;
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state.conditional_code[1] = false;
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#ifdef ARCHITECTURE_x86_64
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#ifdef ARCHITECTURE_x86_64
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if (VideoCore::g_shader_jit_enabled)
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if (VideoCore::g_shader_jit_enabled) {
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jit_shader->Run(setup, state, config.main_offset);
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jit_shader->Run(setup, state, config.main_offset);
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else
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} else {
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RunInterpreter(setup, state, config.main_offset);
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DebugData<false> dummy_debug_data;
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RunInterpreter(setup, state, dummy_debug_data, config.main_offset);
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}
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#else
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#else
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RunInterpreter(setup, state, config.main_offset);
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DebugData<false> dummy_debug_data;
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RunInterpreter(setup, state, dummy_debug_data, config.main_offset);
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#endif // ARCHITECTURE_x86_64
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#endif // ARCHITECTURE_x86_64
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}
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}
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DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_attributes,
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DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_attributes,
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const Regs::ShaderConfig& config,
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const Regs::ShaderConfig& config,
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const ShaderSetup& setup) {
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const ShaderSetup& setup) {
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UnitState<true> state;
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UnitState state;
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DebugData<true> debug_data;
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup input register table
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// Setup input register table
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boost::fill(state.registers.input, Math::Vec4<float24>::AssignToAll(float24::Zero()));
|
boost::fill(state.registers.input, Math::Vec4<float24>::AssignToAll(float24::Zero()));
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@ -154,8 +152,8 @@ DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_
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state.conditional_code[0] = false;
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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state.conditional_code[1] = false;
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|
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RunInterpreter(setup, state, config.main_offset);
|
RunInterpreter(setup, state, debug_data, config.main_offset);
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return state.debug;
|
return debug_data;
|
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}
|
}
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|
|
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} // namespace Shader
|
} // namespace Shader
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@ -8,8 +8,6 @@
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#include <cstddef>
|
#include <cstddef>
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#include <memory>
|
#include <memory>
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#include <type_traits>
|
#include <type_traits>
|
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#include <vector>
|
|
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#include <boost/container/static_vector.hpp>
|
|
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#include <nihstro/shader_bytecode.h>
|
#include <nihstro/shader_bytecode.h>
|
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#include "common/assert.h"
|
#include "common/assert.h"
|
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#include "common/common_funcs.h"
|
#include "common/common_funcs.h"
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@ -17,6 +15,7 @@
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#include "common/vector_math.h"
|
#include "common/vector_math.h"
|
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#include "video_core/pica.h"
|
#include "video_core/pica.h"
|
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#include "video_core/pica_types.h"
|
#include "video_core/pica_types.h"
|
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|
#include "video_core/shader/debug_data.h"
|
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|
|
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using nihstro::RegisterType;
|
using nihstro::RegisterType;
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using nihstro::SourceRegister;
|
using nihstro::SourceRegister;
|
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@ -89,183 +88,12 @@ struct OutputRegisters {
|
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};
|
};
|
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static_assert(std::is_pod<OutputRegisters>::value, "Structure is not POD");
|
static_assert(std::is_pod<OutputRegisters>::value, "Structure is not POD");
|
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|
|
||||||
// Helper structure used to keep track of data useful for inspection of shader emulation
|
|
||||||
template <bool full_debugging>
|
|
||||||
struct DebugData;
|
|
||||||
|
|
||||||
template <>
|
|
||||||
struct DebugData<false> {
|
|
||||||
// TODO: Hide these behind and interface and move them to DebugData<true>
|
|
||||||
u32 max_offset; // maximum program counter ever reached
|
|
||||||
u32 max_opdesc_id; // maximum swizzle pattern index ever used
|
|
||||||
};
|
|
||||||
|
|
||||||
template <>
|
|
||||||
struct DebugData<true> {
|
|
||||||
// Records store the input and output operands of a particular instruction.
|
|
||||||
struct Record {
|
|
||||||
enum Type {
|
|
||||||
// Floating point arithmetic operands
|
|
||||||
SRC1 = 0x1,
|
|
||||||
SRC2 = 0x2,
|
|
||||||
SRC3 = 0x4,
|
|
||||||
|
|
||||||
// Initial and final output operand value
|
|
||||||
DEST_IN = 0x8,
|
|
||||||
DEST_OUT = 0x10,
|
|
||||||
|
|
||||||
// Current and next instruction offset (in words)
|
|
||||||
CUR_INSTR = 0x20,
|
|
||||||
NEXT_INSTR = 0x40,
|
|
||||||
|
|
||||||
// Output address register value
|
|
||||||
ADDR_REG_OUT = 0x80,
|
|
||||||
|
|
||||||
// Result of a comparison instruction
|
|
||||||
CMP_RESULT = 0x100,
|
|
||||||
|
|
||||||
// Input values for conditional flow control instructions
|
|
||||||
COND_BOOL_IN = 0x200,
|
|
||||||
COND_CMP_IN = 0x400,
|
|
||||||
|
|
||||||
// Input values for a loop
|
|
||||||
LOOP_INT_IN = 0x800,
|
|
||||||
};
|
|
||||||
|
|
||||||
Math::Vec4<float24> src1;
|
|
||||||
Math::Vec4<float24> src2;
|
|
||||||
Math::Vec4<float24> src3;
|
|
||||||
|
|
||||||
Math::Vec4<float24> dest_in;
|
|
||||||
Math::Vec4<float24> dest_out;
|
|
||||||
|
|
||||||
s32 address_registers[2];
|
|
||||||
bool conditional_code[2];
|
|
||||||
bool cond_bool;
|
|
||||||
bool cond_cmp[2];
|
|
||||||
Math::Vec4<u8> loop_int;
|
|
||||||
|
|
||||||
u32 instruction_offset;
|
|
||||||
u32 next_instruction;
|
|
||||||
|
|
||||||
// set of enabled fields (as a combination of Type flags)
|
|
||||||
unsigned mask = 0;
|
|
||||||
};
|
|
||||||
|
|
||||||
u32 max_offset; // maximum program counter ever reached
|
|
||||||
u32 max_opdesc_id; // maximum swizzle pattern index ever used
|
|
||||||
|
|
||||||
// List of records for each executed shader instruction
|
|
||||||
std::vector<DebugData<true>::Record> records;
|
|
||||||
};
|
|
||||||
|
|
||||||
// Type alias for better readability
|
|
||||||
using DebugDataRecord = DebugData<true>::Record;
|
|
||||||
|
|
||||||
// Helper function to set a DebugData<true>::Record field based on the template enum parameter.
|
|
||||||
template <DebugDataRecord::Type type, typename ValueType>
|
|
||||||
inline void SetField(DebugDataRecord& record, ValueType value);
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::SRC1>(DebugDataRecord& record, float24* value) {
|
|
||||||
record.src1.x = value[0];
|
|
||||||
record.src1.y = value[1];
|
|
||||||
record.src1.z = value[2];
|
|
||||||
record.src1.w = value[3];
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::SRC2>(DebugDataRecord& record, float24* value) {
|
|
||||||
record.src2.x = value[0];
|
|
||||||
record.src2.y = value[1];
|
|
||||||
record.src2.z = value[2];
|
|
||||||
record.src2.w = value[3];
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::SRC3>(DebugDataRecord& record, float24* value) {
|
|
||||||
record.src3.x = value[0];
|
|
||||||
record.src3.y = value[1];
|
|
||||||
record.src3.z = value[2];
|
|
||||||
record.src3.w = value[3];
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::DEST_IN>(DebugDataRecord& record, float24* value) {
|
|
||||||
record.dest_in.x = value[0];
|
|
||||||
record.dest_in.y = value[1];
|
|
||||||
record.dest_in.z = value[2];
|
|
||||||
record.dest_in.w = value[3];
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::DEST_OUT>(DebugDataRecord& record, float24* value) {
|
|
||||||
record.dest_out.x = value[0];
|
|
||||||
record.dest_out.y = value[1];
|
|
||||||
record.dest_out.z = value[2];
|
|
||||||
record.dest_out.w = value[3];
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::ADDR_REG_OUT>(DebugDataRecord& record, s32* value) {
|
|
||||||
record.address_registers[0] = value[0];
|
|
||||||
record.address_registers[1] = value[1];
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::CMP_RESULT>(DebugDataRecord& record, bool* value) {
|
|
||||||
record.conditional_code[0] = value[0];
|
|
||||||
record.conditional_code[1] = value[1];
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::COND_BOOL_IN>(DebugDataRecord& record, bool value) {
|
|
||||||
record.cond_bool = value;
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::COND_CMP_IN>(DebugDataRecord& record, bool* value) {
|
|
||||||
record.cond_cmp[0] = value[0];
|
|
||||||
record.cond_cmp[1] = value[1];
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::LOOP_INT_IN>(DebugDataRecord& record, Math::Vec4<u8> value) {
|
|
||||||
record.loop_int = value;
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::CUR_INSTR>(DebugDataRecord& record, u32 value) {
|
|
||||||
record.instruction_offset = value;
|
|
||||||
}
|
|
||||||
|
|
||||||
template <>
|
|
||||||
inline void SetField<DebugDataRecord::NEXT_INSTR>(DebugDataRecord& record, u32 value) {
|
|
||||||
record.next_instruction = value;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Helper function to set debug information on the current shader iteration.
|
|
||||||
template <DebugDataRecord::Type type, typename ValueType>
|
|
||||||
inline void Record(DebugData<false>& debug_data, u32 offset, ValueType value) {
|
|
||||||
// Debugging disabled => nothing to do
|
|
||||||
}
|
|
||||||
|
|
||||||
template <DebugDataRecord::Type type, typename ValueType>
|
|
||||||
inline void Record(DebugData<true>& debug_data, u32 offset, ValueType value) {
|
|
||||||
if (offset >= debug_data.records.size())
|
|
||||||
debug_data.records.resize(offset + 1);
|
|
||||||
|
|
||||||
SetField<type, ValueType>(debug_data.records[offset], value);
|
|
||||||
debug_data.records[offset].mask |= type;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* This structure contains the state information that needs to be unique for a shader unit. The 3DS
|
* This structure contains the state information that needs to be unique for a shader unit. The 3DS
|
||||||
* has four shader units that process shaders in parallel. At the present, Citra only implements a
|
* has four shader units that process shaders in parallel. At the present, Citra only implements a
|
||||||
* single shader unit that processes all shaders serially. Putting the state information in a struct
|
* single shader unit that processes all shaders serially. Putting the state information in a struct
|
||||||
* here will make it easier for us to parallelize the shader processing later.
|
* here will make it easier for us to parallelize the shader processing later.
|
||||||
*/
|
*/
|
||||||
template <bool Debug>
|
|
||||||
struct UnitState {
|
struct UnitState {
|
||||||
struct Registers {
|
struct Registers {
|
||||||
// The registers are accessed by the shader JIT using SSE instructions, and are therefore
|
// The registers are accessed by the shader JIT using SSE instructions, and are therefore
|
||||||
@ -283,8 +111,6 @@ struct UnitState {
|
|||||||
// TODO: How many bits do these actually have?
|
// TODO: How many bits do these actually have?
|
||||||
s32 address_registers[3];
|
s32 address_registers[3];
|
||||||
|
|
||||||
DebugData<Debug> debug;
|
|
||||||
|
|
||||||
static size_t InputOffset(const SourceRegister& reg) {
|
static size_t InputOffset(const SourceRegister& reg) {
|
||||||
switch (reg.GetRegisterType()) {
|
switch (reg.GetRegisterType()) {
|
||||||
case RegisterType::Input:
|
case RegisterType::Input:
|
||||||
@ -332,21 +158,16 @@ struct ShaderSetup {
|
|||||||
std::array<Math::Vec4<u8>, 4> i;
|
std::array<Math::Vec4<u8>, 4> i;
|
||||||
} uniforms;
|
} uniforms;
|
||||||
|
|
||||||
static size_t UniformOffset(RegisterType type, unsigned index) {
|
static size_t GetFloatUniformOffset(unsigned index) {
|
||||||
switch (type) {
|
return offsetof(ShaderSetup, uniforms.f) + index * sizeof(Math::Vec4<float24>);
|
||||||
case RegisterType::FloatUniform:
|
}
|
||||||
return offsetof(ShaderSetup, uniforms.f) + index * sizeof(Math::Vec4<float24>);
|
|
||||||
|
|
||||||
case RegisterType::BoolUniform:
|
static size_t GetBoolUniformOffset(unsigned index) {
|
||||||
return offsetof(ShaderSetup, uniforms.b) + index * sizeof(bool);
|
return offsetof(ShaderSetup, uniforms.b) + index * sizeof(bool);
|
||||||
|
}
|
||||||
|
|
||||||
case RegisterType::IntUniform:
|
static size_t GetIntUniformOffset(unsigned index) {
|
||||||
return offsetof(ShaderSetup, uniforms.i) + index * sizeof(Math::Vec4<u8>);
|
return offsetof(ShaderSetup, uniforms.i) + index * sizeof(Math::Vec4<u8>);
|
||||||
|
|
||||||
default:
|
|
||||||
UNREACHABLE();
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
std::array<u32, 1024> program_code;
|
std::array<u32, 1024> program_code;
|
||||||
@ -364,7 +185,7 @@ struct ShaderSetup {
|
|||||||
* @param input Input vertex into the shader
|
* @param input Input vertex into the shader
|
||||||
* @param num_attributes The number of vertex shader attributes
|
* @param num_attributes The number of vertex shader attributes
|
||||||
*/
|
*/
|
||||||
void Run(UnitState<false>& state, const InputVertex& input, int num_attributes);
|
void Run(UnitState& state, const InputVertex& input, int num_attributes);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Produce debug information based on the given shader and input vertex
|
* Produce debug information based on the given shader and input vertex
|
||||||
|
@ -6,6 +6,7 @@
|
|||||||
#include <array>
|
#include <array>
|
||||||
#include <cmath>
|
#include <cmath>
|
||||||
#include <numeric>
|
#include <numeric>
|
||||||
|
#include <boost/container/static_vector.hpp>
|
||||||
#include <nihstro/shader_bytecode.h>
|
#include <nihstro/shader_bytecode.h>
|
||||||
#include "common/assert.h"
|
#include "common/assert.h"
|
||||||
#include "common/common_types.h"
|
#include "common/common_types.h"
|
||||||
@ -38,12 +39,42 @@ struct CallStackElement {
|
|||||||
};
|
};
|
||||||
|
|
||||||
template <bool Debug>
|
template <bool Debug>
|
||||||
void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned offset) {
|
void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData<Debug>& debug_data,
|
||||||
|
unsigned offset) {
|
||||||
// TODO: Is there a maximal size for this?
|
// TODO: Is there a maximal size for this?
|
||||||
boost::container::static_vector<CallStackElement, 16> call_stack;
|
boost::container::static_vector<CallStackElement, 16> call_stack;
|
||||||
|
|
||||||
u32 program_counter = offset;
|
u32 program_counter = offset;
|
||||||
|
|
||||||
|
auto call = [&program_counter, &call_stack](u32 offset, u32 num_instructions, u32 return_offset,
|
||||||
|
u8 repeat_count, u8 loop_increment) {
|
||||||
|
// -1 to make sure when incrementing the PC we end up at the correct offset
|
||||||
|
program_counter = offset - 1;
|
||||||
|
ASSERT(call_stack.size() < call_stack.capacity());
|
||||||
|
call_stack.push_back(
|
||||||
|
{offset + num_instructions, return_offset, repeat_count, loop_increment, offset});
|
||||||
|
};
|
||||||
|
|
||||||
|
auto evaluate_condition = [&state](Instruction::FlowControlType flow_control) {
|
||||||
|
using Op = Instruction::FlowControlType::Op;
|
||||||
|
|
||||||
|
bool result_x = flow_control.refx.Value() == state.conditional_code[0];
|
||||||
|
bool result_y = flow_control.refy.Value() == state.conditional_code[1];
|
||||||
|
|
||||||
|
switch (flow_control.op) {
|
||||||
|
case Op::Or:
|
||||||
|
return result_x || result_y;
|
||||||
|
case Op::And:
|
||||||
|
return result_x && result_y;
|
||||||
|
case Op::JustX:
|
||||||
|
return result_x;
|
||||||
|
case Op::JustY:
|
||||||
|
return result_y;
|
||||||
|
default:
|
||||||
|
UNREACHABLE();
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
const auto& uniforms = g_state.vs.uniforms;
|
const auto& uniforms = g_state.vs.uniforms;
|
||||||
const auto& swizzle_data = g_state.vs.swizzle_data;
|
const auto& swizzle_data = g_state.vs.swizzle_data;
|
||||||
const auto& program_code = g_state.vs.program_code;
|
const auto& program_code = g_state.vs.program_code;
|
||||||
@ -74,20 +105,11 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
const Instruction instr = {program_code[program_counter]};
|
const Instruction instr = {program_code[program_counter]};
|
||||||
const SwizzlePattern swizzle = {swizzle_data[instr.common.operand_desc_id]};
|
const SwizzlePattern swizzle = {swizzle_data[instr.common.operand_desc_id]};
|
||||||
|
|
||||||
auto call = [&program_counter, &call_stack](UnitState<Debug>& state, u32 offset,
|
Record<DebugDataRecord::CUR_INSTR>(debug_data, iteration, program_counter);
|
||||||
u32 num_instructions, u32 return_offset,
|
|
||||||
u8 repeat_count, u8 loop_increment) {
|
|
||||||
// -1 to make sure when incrementing the PC we end up at the correct offset
|
|
||||||
program_counter = offset - 1;
|
|
||||||
ASSERT(call_stack.size() < call_stack.capacity());
|
|
||||||
call_stack.push_back(
|
|
||||||
{offset + num_instructions, return_offset, repeat_count, loop_increment, offset});
|
|
||||||
};
|
|
||||||
Record<DebugDataRecord::CUR_INSTR>(state.debug, iteration, program_counter);
|
|
||||||
if (iteration > 0)
|
if (iteration > 0)
|
||||||
Record<DebugDataRecord::NEXT_INSTR>(state.debug, iteration - 1, program_counter);
|
Record<DebugDataRecord::NEXT_INSTR>(debug_data, iteration - 1, program_counter);
|
||||||
|
|
||||||
state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + program_counter);
|
debug_data.max_offset = std::max<u32>(debug_data.max_offset, 1 + program_counter);
|
||||||
|
|
||||||
auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
|
auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
|
||||||
switch (source_reg.GetRegisterType()) {
|
switch (source_reg.GetRegisterType()) {
|
||||||
@ -155,54 +177,54 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
|
? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
|
||||||
: dummy_vec4_float24;
|
: dummy_vec4_float24;
|
||||||
|
|
||||||
state.debug.max_opdesc_id =
|
debug_data.max_opdesc_id =
|
||||||
std::max<u32>(state.debug.max_opdesc_id, 1 + instr.common.operand_desc_id);
|
std::max<u32>(debug_data.max_opdesc_id, 1 + instr.common.operand_desc_id);
|
||||||
|
|
||||||
switch (instr.opcode.Value().EffectiveOpCode()) {
|
switch (instr.opcode.Value().EffectiveOpCode()) {
|
||||||
case OpCode::Id::ADD: {
|
case OpCode::Id::ADD: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
dest[i] = src1[i] + src2[i];
|
dest[i] = src1[i] + src2[i];
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
case OpCode::Id::MUL: {
|
case OpCode::Id::MUL: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
dest[i] = src1[i] * src2[i];
|
dest[i] = src1[i] * src2[i];
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
case OpCode::Id::FLR:
|
case OpCode::Id::FLR:
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32()));
|
dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32()));
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::MAX:
|
case OpCode::Id::MAX:
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
@ -212,13 +234,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
// max(NaN, 0) -> 0
|
// max(NaN, 0) -> 0
|
||||||
dest[i] = (src1[i] > src2[i]) ? src1[i] : src2[i];
|
dest[i] = (src1[i] > src2[i]) ? src1[i] : src2[i];
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::MIN:
|
case OpCode::Id::MIN:
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
@ -228,16 +250,16 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
// min(NaN, 0) -> 0
|
// min(NaN, 0) -> 0
|
||||||
dest[i] = (src1[i] < src2[i]) ? src1[i] : src2[i];
|
dest[i] = (src1[i] < src2[i]) ? src1[i] : src2[i];
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::DP3:
|
case OpCode::Id::DP3:
|
||||||
case OpCode::Id::DP4:
|
case OpCode::Id::DP4:
|
||||||
case OpCode::Id::DPH:
|
case OpCode::Id::DPH:
|
||||||
case OpCode::Id::DPHI: {
|
case OpCode::Id::DPHI: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
|
|
||||||
OpCode::Id opcode = instr.opcode.Value().EffectiveOpCode();
|
OpCode::Id opcode = instr.opcode.Value().EffectiveOpCode();
|
||||||
if (opcode == OpCode::Id::DPH || opcode == OpCode::Id::DPHI)
|
if (opcode == OpCode::Id::DPH || opcode == OpCode::Id::DPHI)
|
||||||
@ -253,14 +275,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
|
|
||||||
dest[i] = dot;
|
dest[i] = dot;
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Reciprocal
|
// Reciprocal
|
||||||
case OpCode::Id::RCP: {
|
case OpCode::Id::RCP: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
float24 rcp_res = float24::FromFloat32(1.0f / src1[0].ToFloat32());
|
float24 rcp_res = float24::FromFloat32(1.0f / src1[0].ToFloat32());
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
@ -268,14 +290,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
|
|
||||||
dest[i] = rcp_res;
|
dest[i] = rcp_res;
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Reciprocal Square Root
|
// Reciprocal Square Root
|
||||||
case OpCode::Id::RSQ: {
|
case OpCode::Id::RSQ: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
float24 rsq_res = float24::FromFloat32(1.0f / std::sqrt(src1[0].ToFloat32()));
|
float24 rsq_res = float24::FromFloat32(1.0f / std::sqrt(src1[0].ToFloat32()));
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
@ -283,12 +305,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
|
|
||||||
dest[i] = rsq_res;
|
dest[i] = rsq_res;
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
case OpCode::Id::MOVA: {
|
case OpCode::Id::MOVA: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
for (int i = 0; i < 2; ++i) {
|
for (int i = 0; i < 2; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
@ -296,29 +318,29 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
// TODO: Figure out how the rounding is done on hardware
|
// TODO: Figure out how the rounding is done on hardware
|
||||||
state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32());
|
state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32());
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::ADDR_REG_OUT>(state.debug, iteration,
|
Record<DebugDataRecord::ADDR_REG_OUT>(debug_data, iteration,
|
||||||
state.address_registers);
|
state.address_registers);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
case OpCode::Id::MOV: {
|
case OpCode::Id::MOV: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
dest[i] = src1[i];
|
dest[i] = src1[i];
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
case OpCode::Id::SGE:
|
case OpCode::Id::SGE:
|
||||||
case OpCode::Id::SGEI:
|
case OpCode::Id::SGEI:
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
@ -326,14 +348,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
dest[i] = (src1[i] >= src2[i]) ? float24::FromFloat32(1.0f)
|
dest[i] = (src1[i] >= src2[i]) ? float24::FromFloat32(1.0f)
|
||||||
: float24::FromFloat32(0.0f);
|
: float24::FromFloat32(0.0f);
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::SLT:
|
case OpCode::Id::SLT:
|
||||||
case OpCode::Id::SLTI:
|
case OpCode::Id::SLTI:
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
@ -341,12 +363,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f)
|
dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f)
|
||||||
: float24::FromFloat32(0.0f);
|
: float24::FromFloat32(0.0f);
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::CMP:
|
case OpCode::Id::CMP:
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
for (int i = 0; i < 2; ++i) {
|
for (int i = 0; i < 2; ++i) {
|
||||||
// TODO: Can you restrict to one compare via dest masking?
|
// TODO: Can you restrict to one compare via dest masking?
|
||||||
|
|
||||||
@ -383,12 +405,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::CMP_RESULT>(state.debug, iteration, state.conditional_code);
|
Record<DebugDataRecord::CMP_RESULT>(debug_data, iteration, state.conditional_code);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::EX2: {
|
case OpCode::Id::EX2: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
|
|
||||||
// EX2 only takes first component exp2 and writes it to all dest components
|
// EX2 only takes first component exp2 and writes it to all dest components
|
||||||
float24 ex2_res = float24::FromFloat32(std::exp2(src1[0].ToFloat32()));
|
float24 ex2_res = float24::FromFloat32(std::exp2(src1[0].ToFloat32()));
|
||||||
@ -399,13 +421,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
dest[i] = ex2_res;
|
dest[i] = ex2_res;
|
||||||
}
|
}
|
||||||
|
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
case OpCode::Id::LG2: {
|
case OpCode::Id::LG2: {
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
|
|
||||||
// LG2 only takes the first component log2 and writes it to all dest components
|
// LG2 only takes the first component log2 and writes it to all dest components
|
||||||
float24 lg2_res = float24::FromFloat32(std::log2(src1[0].ToFloat32()));
|
float24 lg2_res = float24::FromFloat32(std::log2(src1[0].ToFloat32()));
|
||||||
@ -416,7 +438,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
dest[i] = lg2_res;
|
dest[i] = lg2_res;
|
||||||
}
|
}
|
||||||
|
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -498,17 +520,17 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
|
? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
|
||||||
: dummy_vec4_float24;
|
: dummy_vec4_float24;
|
||||||
|
|
||||||
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
||||||
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
||||||
Record<DebugDataRecord::SRC3>(state.debug, iteration, src3);
|
Record<DebugDataRecord::SRC3>(debug_data, iteration, src3);
|
||||||
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
||||||
for (int i = 0; i < 4; ++i) {
|
for (int i = 0; i < 4; ++i) {
|
||||||
if (!swizzle.DestComponentEnabled(i))
|
if (!swizzle.DestComponentEnabled(i))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
dest[i] = src1[i] * src2[i] + src3[i];
|
dest[i] = src1[i] * src2[i] + src3[i];
|
||||||
}
|
}
|
||||||
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
||||||
} else {
|
} else {
|
||||||
LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
|
LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
|
||||||
(int)instr.opcode.Value().EffectiveOpCode(),
|
(int)instr.opcode.Value().EffectiveOpCode(),
|
||||||
@ -518,26 +540,6 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
}
|
}
|
||||||
|
|
||||||
default: {
|
default: {
|
||||||
static auto evaluate_condition = [](const UnitState<Debug>& state, bool refx, bool refy,
|
|
||||||
Instruction::FlowControlType flow_control) {
|
|
||||||
bool results[2] = {refx == state.conditional_code[0],
|
|
||||||
refy == state.conditional_code[1]};
|
|
||||||
|
|
||||||
switch (flow_control.op) {
|
|
||||||
case flow_control.Or:
|
|
||||||
return results[0] || results[1];
|
|
||||||
|
|
||||||
case flow_control.And:
|
|
||||||
return results[0] && results[1];
|
|
||||||
|
|
||||||
case flow_control.JustX:
|
|
||||||
return results[0];
|
|
||||||
|
|
||||||
case flow_control.JustY:
|
|
||||||
return results[1];
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
// Handle each instruction on its own
|
// Handle each instruction on its own
|
||||||
switch (instr.opcode.Value()) {
|
switch (instr.opcode.Value()) {
|
||||||
case OpCode::Id::END:
|
case OpCode::Id::END:
|
||||||
@ -545,17 +547,15 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::JMPC:
|
case OpCode::Id::JMPC:
|
||||||
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
||||||
state.conditional_code);
|
if (evaluate_condition(instr.flow_control)) {
|
||||||
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy,
|
|
||||||
instr.flow_control)) {
|
|
||||||
program_counter = instr.flow_control.dest_offset - 1;
|
program_counter = instr.flow_control.dest_offset - 1;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::JMPU:
|
case OpCode::Id::JMPU:
|
||||||
Record<DebugDataRecord::COND_BOOL_IN>(
|
Record<DebugDataRecord::COND_BOOL_IN>(
|
||||||
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||||
|
|
||||||
if (uniforms.b[instr.flow_control.bool_uniform_id] ==
|
if (uniforms.b[instr.flow_control.bool_uniform_id] ==
|
||||||
!(instr.flow_control.num_instructions & 1)) {
|
!(instr.flow_control.num_instructions & 1)) {
|
||||||
@ -564,25 +564,23 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::CALL:
|
case OpCode::Id::CALL:
|
||||||
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
||||||
program_counter + 1, 0, 0);
|
program_counter + 1, 0, 0);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::CALLU:
|
case OpCode::Id::CALLU:
|
||||||
Record<DebugDataRecord::COND_BOOL_IN>(
|
Record<DebugDataRecord::COND_BOOL_IN>(
|
||||||
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||||
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
||||||
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
||||||
program_counter + 1, 0, 0);
|
program_counter + 1, 0, 0);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OpCode::Id::CALLC:
|
case OpCode::Id::CALLC:
|
||||||
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
||||||
state.conditional_code);
|
if (evaluate_condition(instr.flow_control)) {
|
||||||
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy,
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
||||||
instr.flow_control)) {
|
|
||||||
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
||||||
program_counter + 1, 0, 0);
|
program_counter + 1, 0, 0);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
@ -592,14 +590,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
|
|
||||||
case OpCode::Id::IFU:
|
case OpCode::Id::IFU:
|
||||||
Record<DebugDataRecord::COND_BOOL_IN>(
|
Record<DebugDataRecord::COND_BOOL_IN>(
|
||||||
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
||||||
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
||||||
call(state, program_counter + 1,
|
call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1,
|
||||||
instr.flow_control.dest_offset - program_counter - 1,
|
|
||||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
||||||
0);
|
0);
|
||||||
} else {
|
} else {
|
||||||
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
||||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
||||||
0);
|
0);
|
||||||
}
|
}
|
||||||
@ -609,16 +606,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
case OpCode::Id::IFC: {
|
case OpCode::Id::IFC: {
|
||||||
// TODO: Do we need to consider swizzlers here?
|
// TODO: Do we need to consider swizzlers here?
|
||||||
|
|
||||||
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
||||||
state.conditional_code);
|
if (evaluate_condition(instr.flow_control)) {
|
||||||
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy,
|
call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1,
|
||||||
instr.flow_control)) {
|
|
||||||
call(state, program_counter + 1,
|
|
||||||
instr.flow_control.dest_offset - program_counter - 1,
|
|
||||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
||||||
0);
|
0);
|
||||||
} else {
|
} else {
|
||||||
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
||||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
||||||
0);
|
0);
|
||||||
}
|
}
|
||||||
@ -633,9 +627,8 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
uniforms.i[instr.flow_control.int_uniform_id].w);
|
uniforms.i[instr.flow_control.int_uniform_id].w);
|
||||||
state.address_registers[2] = loop_param.y;
|
state.address_registers[2] = loop_param.y;
|
||||||
|
|
||||||
Record<DebugDataRecord::LOOP_INT_IN>(state.debug, iteration, loop_param);
|
Record<DebugDataRecord::LOOP_INT_IN>(debug_data, iteration, loop_param);
|
||||||
call(state, program_counter + 1,
|
call(program_counter + 1, instr.flow_control.dest_offset - program_counter + 1,
|
||||||
instr.flow_control.dest_offset - program_counter + 1,
|
|
||||||
instr.flow_control.dest_offset + 1, loop_param.x, loop_param.z);
|
instr.flow_control.dest_offset + 1, loop_param.x, loop_param.z);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -657,8 +650,8 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|||||||
}
|
}
|
||||||
|
|
||||||
// Explicit instantiation
|
// Explicit instantiation
|
||||||
template void RunInterpreter(const ShaderSetup& setup, UnitState<false>& state, unsigned offset);
|
template void RunInterpreter(const ShaderSetup&, UnitState&, DebugData<false>&, unsigned offset);
|
||||||
template void RunInterpreter(const ShaderSetup& setup, UnitState<true>& state, unsigned offset);
|
template void RunInterpreter(const ShaderSetup&, UnitState&, DebugData<true>&, unsigned offset);
|
||||||
|
|
||||||
} // namespace
|
} // namespace
|
||||||
|
|
||||||
|
@ -8,11 +8,14 @@ namespace Pica {
|
|||||||
|
|
||||||
namespace Shader {
|
namespace Shader {
|
||||||
|
|
||||||
template <bool Debug>
|
|
||||||
struct UnitState;
|
struct UnitState;
|
||||||
|
|
||||||
template <bool Debug>
|
template <bool Debug>
|
||||||
void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned offset);
|
struct DebugData;
|
||||||
|
|
||||||
|
template <bool Debug>
|
||||||
|
void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData<Debug>& debug_data,
|
||||||
|
unsigned offset);
|
||||||
|
|
||||||
} // namespace
|
} // namespace
|
||||||
|
|
||||||
|
@ -185,10 +185,10 @@ void JitShader::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRe
|
|||||||
|
|
||||||
if (src_reg.GetRegisterType() == RegisterType::FloatUniform) {
|
if (src_reg.GetRegisterType() == RegisterType::FloatUniform) {
|
||||||
src_ptr = SETUP;
|
src_ptr = SETUP;
|
||||||
src_offset = ShaderSetup::UniformOffset(RegisterType::FloatUniform, src_reg.GetIndex());
|
src_offset = ShaderSetup::GetFloatUniformOffset(src_reg.GetIndex());
|
||||||
} else {
|
} else {
|
||||||
src_ptr = STATE;
|
src_ptr = STATE;
|
||||||
src_offset = UnitState<false>::InputOffset(src_reg);
|
src_offset = UnitState::InputOffset(src_reg);
|
||||||
}
|
}
|
||||||
|
|
||||||
int src_offset_disp = (int)src_offset;
|
int src_offset_disp = (int)src_offset;
|
||||||
@ -266,9 +266,7 @@ void JitShader::Compile_DestEnable(Instruction instr, Xmm src) {
|
|||||||
|
|
||||||
SwizzlePattern swiz = {g_state.vs.swizzle_data[operand_desc_id]};
|
SwizzlePattern swiz = {g_state.vs.swizzle_data[operand_desc_id]};
|
||||||
|
|
||||||
int dest_offset_disp = (int)UnitState<false>::OutputOffset(dest);
|
size_t dest_offset_disp = UnitState::OutputOffset(dest);
|
||||||
ASSERT_MSG(dest_offset_disp == UnitState<false>::OutputOffset(dest),
|
|
||||||
"Destinaton offset too large for int type");
|
|
||||||
|
|
||||||
// If all components are enabled, write the result to the destination register
|
// If all components are enabled, write the result to the destination register
|
||||||
if (swiz.dest_mask == NO_DEST_REG_MASK) {
|
if (swiz.dest_mask == NO_DEST_REG_MASK) {
|
||||||
@ -348,8 +346,7 @@ void JitShader::Compile_EvaluateCondition(Instruction instr) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void JitShader::Compile_UniformCondition(Instruction instr) {
|
void JitShader::Compile_UniformCondition(Instruction instr) {
|
||||||
size_t offset =
|
size_t offset = ShaderSetup::GetBoolUniformOffset(instr.flow_control.bool_uniform_id);
|
||||||
ShaderSetup::UniformOffset(RegisterType::BoolUniform, instr.flow_control.bool_uniform_id);
|
|
||||||
cmp(byte[SETUP + offset], 0);
|
cmp(byte[SETUP + offset], 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -732,8 +729,7 @@ void JitShader::Compile_LOOP(Instruction instr) {
|
|||||||
// This decodes the fields from the integer uniform at index instr.flow_control.int_uniform_id.
|
// This decodes the fields from the integer uniform at index instr.flow_control.int_uniform_id.
|
||||||
// The Y (LOOPCOUNT_REG) and Z (LOOPINC) component are kept multiplied by 16 (Left shifted by
|
// The Y (LOOPCOUNT_REG) and Z (LOOPINC) component are kept multiplied by 16 (Left shifted by
|
||||||
// 4 bits) to be used as an offset into the 16-byte vector registers later
|
// 4 bits) to be used as an offset into the 16-byte vector registers later
|
||||||
size_t offset =
|
size_t offset = ShaderSetup::GetIntUniformOffset(instr.flow_control.int_uniform_id);
|
||||||
ShaderSetup::UniformOffset(RegisterType::IntUniform, instr.flow_control.int_uniform_id);
|
|
||||||
mov(LOOPCOUNT, dword[SETUP + offset]);
|
mov(LOOPCOUNT, dword[SETUP + offset]);
|
||||||
mov(LOOPCOUNT_REG, LOOPCOUNT);
|
mov(LOOPCOUNT_REG, LOOPCOUNT);
|
||||||
shr(LOOPCOUNT_REG, 4);
|
shr(LOOPCOUNT_REG, 4);
|
||||||
|
@ -34,7 +34,7 @@ class JitShader : public Xbyak::CodeGenerator {
|
|||||||
public:
|
public:
|
||||||
JitShader();
|
JitShader();
|
||||||
|
|
||||||
void Run(const ShaderSetup& setup, UnitState<false>& state, unsigned offset) const {
|
void Run(const ShaderSetup& setup, UnitState& state, unsigned offset) const {
|
||||||
program(&setup, &state, instruction_labels[offset].getAddress());
|
program(&setup, &state, instruction_labels[offset].getAddress());
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user