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Fix BLX LR opcode interpretation
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parent
a4c5d8fd50
commit
2efc1c9348
@ -4080,11 +4080,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
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if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
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unsigned int inst = inst_cream->inst;
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unsigned int inst = inst_cream->inst;
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if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
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if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
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const u32 jump_address = cpu->Reg[inst_cream->val.Rm];
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cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
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cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
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if(cpu->TFlag)
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if(cpu->TFlag)
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cpu->Reg[14] |= 0x1;
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cpu->Reg[14] |= 0x1;
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cpu->Reg[15] = cpu->Reg[inst_cream->val.Rm] & 0xfffffffe;
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cpu->Reg[15] = jump_address & 0xfffffffe;
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cpu->TFlag = cpu->Reg[inst_cream->val.Rm] & 0x1;
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cpu->TFlag = jump_address & 0x1;
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} else {
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} else {
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cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
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cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
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cpu->TFlag = 0x1;
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cpu->TFlag = 0x1;
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