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OpenGL: Respect buffer-write allow registers
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c6bbc41984
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@ -290,6 +290,19 @@ void RasterizerOpenGL::NotifyPicaRegisterChanged(u32 id) {
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SyncColorWriteMask();
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SyncColorWriteMask();
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break;
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break;
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// Sync GL depth and stencil write mask
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// (This is a dedicated combined depth / stencil write-enable register)
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case PICA_REG_INDEX(framebuffer.allow_depth_stencil_write):
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SyncDepthWriteMask();
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SyncStencilWriteMask();
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break;
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// Sync GL color write mask
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// (This is a dedicated color write-enable register)
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case PICA_REG_INDEX(framebuffer.allow_color_write):
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SyncColorWriteMask();
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break;
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// Logic op
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// Logic op
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case PICA_REG_INDEX(output_merger.logic_op):
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case PICA_REG_INDEX(output_merger.logic_op):
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SyncLogicOp();
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SyncLogicOp();
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@ -893,20 +906,29 @@ void RasterizerOpenGL::SyncLogicOp() {
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void RasterizerOpenGL::SyncColorWriteMask() {
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void RasterizerOpenGL::SyncColorWriteMask() {
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const auto& regs = Pica::g_state.regs;
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const auto& regs = Pica::g_state.regs;
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state.color_mask.red_enabled = regs.output_merger.red_enable;
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state.color_mask.green_enabled = regs.output_merger.green_enable;
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auto IsColorWriteEnabled = [&](u32 value) {
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state.color_mask.blue_enabled = regs.output_merger.blue_enable;
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return (regs.framebuffer.allow_color_write != 0 && value != 0) ? GL_TRUE : GL_FALSE;
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state.color_mask.alpha_enabled = regs.output_merger.alpha_enable;
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};
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state.color_mask.red_enabled = IsColorWriteEnabled(regs.output_merger.red_enable);
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state.color_mask.green_enabled = IsColorWriteEnabled(regs.output_merger.green_enable);
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state.color_mask.blue_enabled = IsColorWriteEnabled(regs.output_merger.blue_enable);
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state.color_mask.alpha_enabled = IsColorWriteEnabled(regs.output_merger.alpha_enable);
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}
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}
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void RasterizerOpenGL::SyncStencilWriteMask() {
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void RasterizerOpenGL::SyncStencilWriteMask() {
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const auto& regs = Pica::g_state.regs;
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const auto& regs = Pica::g_state.regs;
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state.stencil.write_mask = regs.output_merger.stencil_test.write_mask;
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state.stencil.write_mask = (regs.framebuffer.allow_depth_stencil_write != 0)
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? static_cast<GLuint>(regs.output_merger.stencil_test.write_mask)
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: 0;
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}
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}
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void RasterizerOpenGL::SyncDepthWriteMask() {
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void RasterizerOpenGL::SyncDepthWriteMask() {
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const auto& regs = Pica::g_state.regs;
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const auto& regs = Pica::g_state.regs;
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state.depth.write_mask = regs.output_merger.depth_write_enable ? GL_TRUE : GL_FALSE;
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state.depth.write_mask = (regs.framebuffer.allow_depth_stencil_write != 0 && regs.output_merger.depth_write_enable)
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? GL_TRUE
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: GL_FALSE;
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}
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}
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void RasterizerOpenGL::SyncStencilTest() {
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void RasterizerOpenGL::SyncStencilTest() {
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