mirror of
https://github.com/citra-mirror/citra.git
synced 2024-08-24 21:27:19 +02:00
ARM: Add a mechanism for faking CPU time elapsed during HLE.
- Also a few cleanups.
This commit is contained in:
parent
5241e7a9c3
commit
4783133bbd
@ -77,6 +77,12 @@ public:
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*/
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*/
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virtual u64 GetTicks() const = 0;
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virtual u64 GetTicks() const = 0;
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/**
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* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
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* @param ticks Number of ticks to advance the CPU core
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*/
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virtual void AddTicks(u64 ticks) = 0;
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/**
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/**
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* Saves the current CPU context
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* Saves the current CPU context
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* @param ctx Thread context to save
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* @param ctx Thread context to save
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@ -47,68 +47,38 @@ ARM_DynCom::ARM_DynCom() : ticks(0) {
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ARM_DynCom::~ARM_DynCom() {
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ARM_DynCom::~ARM_DynCom() {
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}
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}
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/**
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* Set the Program Counter to an address
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* @param addr Address to set PC to
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*/
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void ARM_DynCom::SetPC(u32 pc) {
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void ARM_DynCom::SetPC(u32 pc) {
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state->pc = state->Reg[15] = pc;
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state->pc = state->Reg[15] = pc;
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}
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}
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/*
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* Get the current Program Counter
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* @return Returns current PC
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*/
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u32 ARM_DynCom::GetPC() const {
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u32 ARM_DynCom::GetPC() const {
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return state->Reg[15];
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return state->Reg[15];
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}
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}
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/**
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* Get an ARM register
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* @param index Register index (0-15)
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* @return Returns the value in the register
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*/
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u32 ARM_DynCom::GetReg(int index) const {
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u32 ARM_DynCom::GetReg(int index) const {
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return state->Reg[index];
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return state->Reg[index];
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}
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}
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/**
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* Set an ARM register
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* @param index Register index (0-15)
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* @param value Value to set register to
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*/
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void ARM_DynCom::SetReg(int index, u32 value) {
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void ARM_DynCom::SetReg(int index, u32 value) {
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state->Reg[index] = value;
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state->Reg[index] = value;
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}
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}
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/**
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* Get the current CPSR register
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* @return Returns the value of the CPSR register
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*/
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u32 ARM_DynCom::GetCPSR() const {
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u32 ARM_DynCom::GetCPSR() const {
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return state->Cpsr;
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return state->Cpsr;
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}
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}
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/**
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* Set the current CPSR register
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* @param cpsr Value to set CPSR to
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*/
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void ARM_DynCom::SetCPSR(u32 cpsr) {
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void ARM_DynCom::SetCPSR(u32 cpsr) {
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state->Cpsr = cpsr;
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state->Cpsr = cpsr;
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}
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}
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/**
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* Returns the number of clock ticks since the last reset
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* @return Returns number of clock ticks
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*/
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u64 ARM_DynCom::GetTicks() const {
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u64 ARM_DynCom::GetTicks() const {
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return ticks;
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return ticks;
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}
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}
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/**
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void ARM_DynCom::AddTicks(u64 ticks) {
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* Executes the given number of instructions
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this->ticks += ticks;
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* @param num_instructions Number of instructions to executes
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}
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*/
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void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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state->NumInstrsToExecute = num_instructions;
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state->NumInstrsToExecute = num_instructions;
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@ -118,11 +88,6 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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ticks += InterpreterMainLoop(state.get());
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ticks += InterpreterMainLoop(state.get());
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}
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}
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/**
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* Saves the current CPU context
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* @param ctx Thread context to save
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* @todo Do we need to save Reg[15] and NextInstr?
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*/
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void ARM_DynCom::SaveContext(ThreadContext& ctx) {
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void ARM_DynCom::SaveContext(ThreadContext& ctx) {
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
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@ -139,11 +104,6 @@ void ARM_DynCom::SaveContext(ThreadContext& ctx) {
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ctx.mode = state->NextInstr;
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ctx.mode = state->NextInstr;
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}
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}
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/**
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* Loads a CPU context
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* @param ctx Thread context to load
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* @param Do we need to load Reg[15] and NextInstr?
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*/
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void ARM_DynCom::LoadContext(const ThreadContext& ctx) {
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void ARM_DynCom::LoadContext(const ThreadContext& ctx) {
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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@ -160,7 +120,6 @@ void ARM_DynCom::LoadContext(const ThreadContext& ctx) {
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state->NextInstr = ctx.mode;
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state->NextInstr = ctx.mode;
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}
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}
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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void ARM_DynCom::PrepareReschedule() {
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void ARM_DynCom::PrepareReschedule() {
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state->NumInstrsToExecute = 0;
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state->NumInstrsToExecute = 0;
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}
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}
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@ -27,14 +27,14 @@ public:
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* Get the current Program Counter
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* Get the current Program Counter
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* @return Returns current PC
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* @return Returns current PC
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*/
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*/
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u32 GetPC() const;
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u32 GetPC() const override;
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/**
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/**
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* Get an ARM register
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* Get an ARM register
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* @param index Register index (0-15)
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* @param index Register index (0-15)
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* @return Returns the value in the register
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* @return Returns the value in the register
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*/
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*/
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u32 GetReg(int index) const;
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u32 GetReg(int index) const override;
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/**
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/**
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* Set an ARM register
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* Set an ARM register
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@ -47,7 +47,7 @@ public:
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* Get the current CPSR register
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* Get the current CPSR register
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* @return Returns the value of the CPSR register
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* @return Returns the value of the CPSR register
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*/
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*/
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u32 GetCPSR() const;
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u32 GetCPSR() const override;
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/**
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/**
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* Set the current CPSR register
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* Set the current CPSR register
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@ -59,7 +59,13 @@ public:
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* Returns the number of clock ticks since the last reset
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* Returns the number of clock ticks since the last reset
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* @return Returns number of clock ticks
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* @return Returns number of clock ticks
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*/
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*/
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u64 GetTicks() const;
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u64 GetTicks() const override;
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/**
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* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
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* @param ticks Number of ticks to advance the CPU core
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*/
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void AddTicks(u64 ticks) override;
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/**
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/**
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* Saves the current CPU context
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* Saves the current CPU context
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@ -38,78 +38,43 @@ ARM_Interpreter::~ARM_Interpreter() {
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delete state;
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delete state;
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}
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}
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/**
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* Set the Program Counter to an address
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* @param addr Address to set PC to
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*/
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void ARM_Interpreter::SetPC(u32 pc) {
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void ARM_Interpreter::SetPC(u32 pc) {
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state->pc = state->Reg[15] = pc;
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state->pc = state->Reg[15] = pc;
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}
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}
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/*
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* Get the current Program Counter
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* @return Returns current PC
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*/
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u32 ARM_Interpreter::GetPC() const {
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u32 ARM_Interpreter::GetPC() const {
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return state->pc;
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return state->pc;
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}
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}
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/**
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* Get an ARM register
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* @param index Register index (0-15)
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* @return Returns the value in the register
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*/
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u32 ARM_Interpreter::GetReg(int index) const {
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u32 ARM_Interpreter::GetReg(int index) const {
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return state->Reg[index];
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return state->Reg[index];
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}
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}
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/**
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* Set an ARM register
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* @param index Register index (0-15)
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* @param value Value to set register to
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*/
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void ARM_Interpreter::SetReg(int index, u32 value) {
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void ARM_Interpreter::SetReg(int index, u32 value) {
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state->Reg[index] = value;
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state->Reg[index] = value;
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}
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}
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/**
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* Get the current CPSR register
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* @return Returns the value of the CPSR register
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*/
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u32 ARM_Interpreter::GetCPSR() const {
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u32 ARM_Interpreter::GetCPSR() const {
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return state->Cpsr;
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return state->Cpsr;
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}
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}
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/**
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* Set the current CPSR register
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* @param cpsr Value to set CPSR to
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*/
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void ARM_Interpreter::SetCPSR(u32 cpsr) {
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void ARM_Interpreter::SetCPSR(u32 cpsr) {
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state->Cpsr = cpsr;
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state->Cpsr = cpsr;
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}
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}
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/**
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* Returns the number of clock ticks since the last reset
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* @return Returns number of clock ticks
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*/
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u64 ARM_Interpreter::GetTicks() const {
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u64 ARM_Interpreter::GetTicks() const {
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return ARMul_Time(state);
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return state->NumInstrs;
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}
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void ARM_Interpreter::AddTicks(u64 ticks) {
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state->NumInstrs += ticks;
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}
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}
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/**
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* Executes the given number of instructions
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* @param num_instructions Number of instructions to executes
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*/
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void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
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void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
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state->NumInstrsToExecute = num_instructions - 1;
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state->NumInstrsToExecute = num_instructions - 1;
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ARMul_Emulate32(state);
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ARMul_Emulate32(state);
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}
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}
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/**
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* Saves the current CPU context
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* @param ctx Thread context to save
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* @todo Do we need to save Reg[15] and NextInstr?
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*/
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void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
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void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
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@ -126,11 +91,6 @@ void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
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ctx.mode = state->NextInstr;
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ctx.mode = state->NextInstr;
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}
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}
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/**
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* Loads a CPU context
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* @param ctx Thread context to load
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* @param Do we need to load Reg[15] and NextInstr?
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*/
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void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
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void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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@ -147,7 +107,6 @@ void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
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state->NextInstr = ctx.mode;
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state->NextInstr = ctx.mode;
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}
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}
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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void ARM_Interpreter::PrepareReschedule() {
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void ARM_Interpreter::PrepareReschedule() {
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state->NumInstrsToExecute = 0;
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state->NumInstrsToExecute = 0;
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}
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}
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@ -60,6 +60,12 @@ public:
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*/
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*/
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u64 GetTicks() const override;
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u64 GetTicks() const override;
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/**
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* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
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* @param ticks Number of ticks to advance the CPU core
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*/
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void AddTicks(u64 ticks) override;
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/**
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/**
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* Saves the current CPU context
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* Saves the current CPU context
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* @param ctx Thread context to save
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* @param ctx Thread context to save
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@ -43,7 +43,15 @@ void CallSVC(u32 opcode) {
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void Reschedule(const char *reason) {
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void Reschedule(const char *reason) {
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_dbg_assert_msg_(Kernel, reason != 0 && strlen(reason) < 256, "Reschedule: Invalid or too long reason.");
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_dbg_assert_msg_(Kernel, reason != 0 && strlen(reason) < 256, "Reschedule: Invalid or too long reason.");
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// TODO(bunnei): It seems that games depend on some CPU execution time elapsing during HLE
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// routines. This simulates that time by artificially advancing the number of CPU "ticks".
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// The value was chosen empirically, it seems to work well enough for everything tested, but
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// is likely not ideal. We should find a more accurate way to simulate timing with HLE.
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Core::g_app_core->AddTicks(4000);
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Core::g_app_core->PrepareReschedule();
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Core::g_app_core->PrepareReschedule();
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g_reschedule = true;
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g_reschedule = true;
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}
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}
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