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https://github.com/citra-mirror/citra.git
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Merge pull request #482 from yuriks/fix-vblank
Correctness fixes for GPU flipping and interrupts
This commit is contained in:
commit
4b47ed6194
@ -210,14 +210,27 @@ void SignalInterrupt(InterruptId interrupt_id) {
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}
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}
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for (int thread_id = 0; thread_id < 0x4; ++thread_id) {
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for (int thread_id = 0; thread_id < 0x4; ++thread_id) {
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InterruptRelayQueue* interrupt_relay_queue = GetInterruptRelayQueue(thread_id);
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InterruptRelayQueue* interrupt_relay_queue = GetInterruptRelayQueue(thread_id);
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interrupt_relay_queue->number_interrupts = interrupt_relay_queue->number_interrupts + 1;
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u8 next = interrupt_relay_queue->index;
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u8 next = interrupt_relay_queue->index;
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next += interrupt_relay_queue->number_interrupts;
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next += interrupt_relay_queue->number_interrupts;
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next = next % 0x34; // 0x34 is the number of interrupt slots
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next = next % 0x34; // 0x34 is the number of interrupt slots
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interrupt_relay_queue->number_interrupts += 1;
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interrupt_relay_queue->slot[next] = interrupt_id;
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interrupt_relay_queue->slot[next] = interrupt_id;
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interrupt_relay_queue->error_code = 0x0; // No error
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interrupt_relay_queue->error_code = 0x0; // No error
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// Update framebuffer information if requested
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// TODO(yuriks): Confirm where this code should be called. It is definitely updated without
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// executing any GSP commands, only waiting on the event.
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for (int screen_id = 0; screen_id < 2; ++screen_id) {
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FrameBufferUpdate* info = GetFrameBufferInfo(thread_id, screen_id);
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if (info->is_dirty) {
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SetBufferSwap(screen_id, info->framebuffer_info[info->index]);
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}
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info->is_dirty = false;
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}
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}
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}
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Kernel::SignalEvent(g_interrupt_event);
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Kernel::SignalEvent(g_interrupt_event);
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}
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}
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@ -269,8 +282,6 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].address_end), Memory::VirtualToPhysicalAddress(params.end2) >> 3);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].address_end), Memory::VirtualToPhysicalAddress(params.end2) >> 3);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].size), params.end2 - params.start2);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].size), params.end2 - params.start2);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].value), params.value2);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].value), params.value2);
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SignalInterrupt(InterruptId::PSC0);
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break;
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break;
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}
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}
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@ -283,22 +294,6 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_size), params.out_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_size), params.out_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.flags), params.flags);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.flags), params.flags);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.trigger), 1);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.trigger), 1);
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// TODO(bunnei): Determine if these interrupts should be signalled here.
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SignalInterrupt(InterruptId::PSC1);
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SignalInterrupt(InterruptId::PPF);
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// Update framebuffer information if requested
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for (int screen_id = 0; screen_id < 2; ++screen_id) {
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FrameBufferUpdate* info = GetFrameBufferInfo(thread_id, screen_id);
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if (info->is_dirty) {
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SetBufferSwap(screen_id, info->framebuffer_info[info->index]);
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info->framebuffer_info->active_fb = info->framebuffer_info->active_fb ^ 1;
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}
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info->is_dirty = false;
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}
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break;
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break;
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}
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}
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@ -45,21 +45,16 @@ enum class CommandId : u32 {
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/// GSP thread interrupt relay queue
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/// GSP thread interrupt relay queue
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struct InterruptRelayQueue {
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struct InterruptRelayQueue {
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union {
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u32 hex;
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// Index of last interrupt in the queue
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// Index of last interrupt in the queue
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BitField<0,8,u32> index;
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u8 index;
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// Number of interrupts remaining to be processed by the userland code
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// Number of interrupts remaining to be processed by the userland code
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BitField<8,8,u32> number_interrupts;
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u8 number_interrupts;
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// Error code - zero on success, otherwise an error has occurred
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// Error code - zero on success, otherwise an error has occurred
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BitField<16,8,u32> error_code;
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u8 error_code;
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};
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u8 padding1;
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u32 unk0;
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u32 missed_PDC0;
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u32 unk1;
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u32 missed_PDC1;
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InterruptId slot[0x34]; ///< Interrupt ID slots
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InterruptId slot[0x34]; ///< Interrupt ID slots
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};
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};
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@ -9,6 +9,7 @@
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#include "core/settings.h"
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#include "core/settings.h"
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#include "core/core.h"
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#include "core/core.h"
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#include "core/mem_map.h"
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#include "core/mem_map.h"
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#include "core/core_timing.h"
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#include "core/hle/hle.h"
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#include "core/hle/hle.h"
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#include "core/hle/service/gsp_gpu.h"
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#include "core/hle/service/gsp_gpu.h"
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@ -24,14 +25,17 @@ namespace GPU {
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Regs g_regs;
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Regs g_regs;
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bool g_skip_frame = false; ///< True if the current frame was skipped
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/// True if the current frame was skipped
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bool g_skip_frame = false;
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static u64 frame_ticks = 0; ///< 268MHz / gpu_refresh_rate frames per second
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/// 268MHz / gpu_refresh_rate frames per second
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static u64 line_ticks = 0; ///< Number of ticks for a screen line
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static u64 frame_ticks;
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static u32 cur_line = 0; ///< Current screen line
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/// Event id for CoreTiming
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static u64 last_update_tick = 0; ///< CPU ticl count from last GPU update
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static int vblank_event;
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static u64 frame_count = 0; ///< Number of frames drawn
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/// Total number of frames drawn
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static bool last_skip_frame = false; ///< True if the last frame was skipped
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static u64 frame_count;
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/// True if the last frame was skipped
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static bool last_skip_frame = false;
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template <typename T>
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template <typename T>
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inline void Read(T &var, const u32 raw_addr) {
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inline void Read(T &var, const u32 raw_addr) {
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@ -79,6 +83,12 @@ inline void Write(u32 addr, const T data) {
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*ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
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*ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
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LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress());
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LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress());
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if (!is_second_filler) {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0);
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} else {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC1);
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}
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}
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}
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break;
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break;
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}
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}
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@ -90,22 +100,25 @@ inline void Write(u32 addr, const T data) {
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u8* source_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalInputAddress()));
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u8* source_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalInputAddress()));
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u8* dest_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalOutputAddress()));
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u8* dest_pointer = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetPhysicalOutputAddress()));
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for (u32 y = 0; y < config.output_height; ++y) {
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// TODO: Why does the register seem to hold twice the framebuffer width?
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for (u32 x = 0; x < config.output_width; ++x) {
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struct {
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int r, g, b, a;
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} source_color = { 0, 0, 0, 0 };
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// Cheap emulation of horizontal scaling: Just skip each second pixel of the
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// Cheap emulation of horizontal scaling: Just skip each second pixel of the
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// input framebuffer. We keep track of this in the pixel_skip variable.
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// input framebuffer. We keep track of this in the pixel_skip variable.
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unsigned pixel_skip = (config.scale_horizontally != 0) ? 2 : 1;
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unsigned pixel_skip = (config.scale_horizontally != 0) ? 2 : 1;
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u32 output_width = config.output_width / pixel_skip;
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for (u32 y = 0; y < config.output_height; ++y) {
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// TODO: Why does the register seem to hold twice the framebuffer width?
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for (u32 x = 0; x < output_width; ++x) {
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struct {
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int r, g, b, a;
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} source_color = { 0, 0, 0, 0 };
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switch (config.input_format) {
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switch (config.input_format) {
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case Regs::PixelFormat::RGBA8:
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case Regs::PixelFormat::RGBA8:
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{
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{
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// TODO: Most likely got the component order messed up.
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// TODO: Most likely got the component order messed up.
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u8* srcptr = source_pointer + x * 4 * pixel_skip + y * config.input_width * 4 * pixel_skip;
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u8* srcptr = source_pointer + (x * pixel_skip + y * config.input_width) * 4;
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source_color.r = srcptr[0]; // blue
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source_color.r = srcptr[0]; // blue
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source_color.g = srcptr[1]; // green
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source_color.g = srcptr[1]; // green
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source_color.b = srcptr[2]; // red
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source_color.b = srcptr[2]; // red
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@ -133,7 +146,7 @@ inline void Write(u32 addr, const T data) {
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case Regs::PixelFormat::RGB8:
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case Regs::PixelFormat::RGB8:
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{
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{
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// TODO: Most likely got the component order messed up.
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// TODO: Most likely got the component order messed up.
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u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3;
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u8* dstptr = dest_pointer + (x + y * output_width) * 3;
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dstptr[0] = source_color.r; // blue
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dstptr[0] = source_color.r; // blue
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dstptr[1] = source_color.g; // green
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dstptr[1] = source_color.g; // green
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dstptr[2] = source_color.b; // red
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dstptr[2] = source_color.b; // red
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@ -148,10 +161,12 @@ inline void Write(u32 addr, const T data) {
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}
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}
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LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> 0x%08x(%ux%u), dst format %x",
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LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> 0x%08x(%ux%u), dst format %x",
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config.output_height * config.output_width * 4,
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config.output_height * output_width * 4,
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config.GetPhysicalInputAddress(), (u32)config.input_width, (u32)config.input_height,
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config.GetPhysicalInputAddress(), (u32)config.input_width, (u32)config.input_height,
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config.GetPhysicalOutputAddress(), (u32)config.output_width, (u32)config.output_height,
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config.GetPhysicalOutputAddress(), (u32)output_width, (u32)config.output_height,
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config.output_format.Value());
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config.output_format.Value());
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF);
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}
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}
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break;
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break;
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}
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}
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@ -186,27 +201,9 @@ template void Write<u16>(u32 addr, const u16 data);
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template void Write<u8>(u32 addr, const u8 data);
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template void Write<u8>(u32 addr, const u8 data);
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/// Update hardware
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/// Update hardware
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void Update() {
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static void VBlankCallback(u64 userdata, int cycles_late) {
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auto& framebuffer_top = g_regs.framebuffer_config[0];
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auto& framebuffer_top = g_regs.framebuffer_config[0];
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// Synchronize GPU on a thread reschedule: Because we cannot accurately predict a vertical
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// blank, we need to simulate it. Based on testing, it seems that retail applications work more
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// accurately when this is signalled between thread switches.
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if (HLE::g_reschedule) {
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u64 current_ticks = Core::g_app_core->GetTicks();
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u32 num_lines = static_cast<u32>((current_ticks - last_update_tick) / line_ticks);
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// Synchronize line...
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if (num_lines > 0) {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PDC0);
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cur_line += num_lines;
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last_update_tick += (num_lines * line_ticks);
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}
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// Synchronize frame...
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if (cur_line >= framebuffer_top.height) {
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cur_line = 0;
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frame_count++;
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frame_count++;
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last_skip_frame = g_skip_frame;
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last_skip_frame = g_skip_frame;
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g_skip_frame = (frame_count & Settings::values.frame_skip) != 0;
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g_skip_frame = (frame_count & Settings::values.frame_skip) != 0;
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@ -223,14 +220,20 @@ void Update() {
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}
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}
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// Signal to GSP that GPU interrupt has occurred
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// Signal to GSP that GPU interrupt has occurred
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// TODO(yuriks): hwtest to determine if PDC0 is for the Top screen and PDC1 for the Sub
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// screen, or if both use the same interrupts and these two instead determine the
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// beginning and end of the VBlank period. If needed, split the interrupt firing into
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// two different intervals.
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PDC0);
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PDC1);
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PDC1);
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// TODO(bunnei): Fake a DSP interrupt on each frame. This does not belong here, but
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// TODO(bunnei): Fake a DSP interrupt on each frame. This does not belong here, but
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// until we can emulate DSP interrupts, this is probably the only reasonable place to do
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// until we can emulate DSP interrupts, this is probably the only reasonable place to do
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// this. Certain games expect this to be periodically signaled.
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// this. Certain games expect this to be periodically signaled.
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DSP_DSP::SignalInterrupt();
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DSP_DSP::SignalInterrupt();
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}
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}
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// Reschedule recurrent event
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CoreTiming::ScheduleEvent(frame_ticks - cycles_late, vblank_event);
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}
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}
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/// Initialize hardware
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/// Initialize hardware
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@ -247,8 +250,8 @@ void Init() {
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framebuffer_top.address_right1 = 0x18273000;
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framebuffer_top.address_right1 = 0x18273000;
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framebuffer_top.address_right2 = 0x182B9800;
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framebuffer_top.address_right2 = 0x182B9800;
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framebuffer_sub.address_left1 = 0x1848F000;
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framebuffer_sub.address_left1 = 0x1848F000;
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//framebuffer_sub.address_left2 = unknown;
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framebuffer_sub.address_left2 = 0x184C7800;
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framebuffer_sub.address_right1 = 0x184C7800;
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//framebuffer_sub.address_right1 = unknown;
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//framebuffer_sub.address_right2 = unknown;
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//framebuffer_sub.address_right2 = unknown;
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framebuffer_top.width = 240;
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framebuffer_top.width = 240;
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@ -264,12 +267,12 @@ void Init() {
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framebuffer_sub.active_fb = 0;
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framebuffer_sub.active_fb = 0;
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frame_ticks = 268123480 / Settings::values.gpu_refresh_rate;
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frame_ticks = 268123480 / Settings::values.gpu_refresh_rate;
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line_ticks = (GPU::frame_ticks / framebuffer_top.height);
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cur_line = 0;
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last_update_tick = Core::g_app_core->GetTicks();
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last_skip_frame = false;
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last_skip_frame = false;
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g_skip_frame = false;
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g_skip_frame = false;
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vblank_event = CoreTiming::RegisterEvent("GPU::VBlankCallback", VBlankCallback);
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CoreTiming::ScheduleEvent(frame_ticks, vblank_event);
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LOG_DEBUG(HW_GPU, "initialized OK");
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LOG_DEBUG(HW_GPU, "initialized OK");
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}
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}
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@ -252,9 +252,6 @@ void Read(T &var, const u32 addr);
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template <typename T>
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template <typename T>
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void Write(u32 addr, const T data);
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void Write(u32 addr, const T data);
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/// Update hardware
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void Update();
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/// Initialize hardware
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/// Initialize hardware
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void Init();
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void Init();
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@ -75,7 +75,6 @@ template void Write<u8>(u32 addr, const u8 data);
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/// Update hardware
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/// Update hardware
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void Update() {
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void Update() {
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GPU::Update();
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}
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}
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/// Initialize hardware
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/// Initialize hardware
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@ -88,10 +88,8 @@ void RendererOpenGL::SwapBuffers() {
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void RendererOpenGL::LoadFBToActiveGLTexture(const GPU::Regs::FramebufferConfig& framebuffer,
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void RendererOpenGL::LoadFBToActiveGLTexture(const GPU::Regs::FramebufferConfig& framebuffer,
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const TextureInfo& texture) {
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const TextureInfo& texture) {
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// TODO: Why are active_fb and the valid framebuffer flipped compared to 3dbrew documentation
|
|
||||||
// and GSP definitions?
|
|
||||||
const VAddr framebuffer_vaddr = Memory::PhysicalToVirtualAddress(
|
const VAddr framebuffer_vaddr = Memory::PhysicalToVirtualAddress(
|
||||||
framebuffer.active_fb == 0 ? framebuffer.address_left2 : framebuffer.address_left1);
|
framebuffer.active_fb == 0 ? framebuffer.address_left1 : framebuffer.address_left2);
|
||||||
|
|
||||||
LOG_TRACE(Render_OpenGL, "0x%08x bytes from 0x%08x(%dx%d), fmt %x",
|
LOG_TRACE(Render_OpenGL, "0x%08x bytes from 0x%08x(%dx%d), fmt %x",
|
||||||
framebuffer.stride * framebuffer.height,
|
framebuffer.stride * framebuffer.height,
|
||||||
|
Loading…
Reference in New Issue
Block a user