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commit
52bc58283d
@ -6327,11 +6327,14 @@ L_stm_s_takeabort:
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}
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}
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case 0x70:
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case 0x70:
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// ichfly
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// ichfly
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// SMUAD, SMUSD, SMLAD
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// SMUAD, SMUSD, SMLAD, and SMLSD
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if ((instr & 0xf0d0) == 0xf010 || (instr & 0xf0d0) == 0xf050 || (instr & 0xd0) == 0x10) {
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if ((instr & 0xf0d0) == 0xf010 || (instr & 0xf0d0) == 0xf050 ||
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(instr & 0xd0) == 0x10 || (instr & 0xd0) == 0x50)
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{
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const u8 rd_idx = BITS(16, 19);
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const u8 rd_idx = BITS(16, 19);
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const u8 rn_idx = BITS(0, 3);
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const u8 rn_idx = BITS(0, 3);
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const u8 rm_idx = BITS(8, 11);
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const u8 rm_idx = BITS(8, 11);
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const u8 ra_idx = BITS(12, 15);
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const bool do_swap = (BIT(5) == 1);
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const bool do_swap = (BIT(5) == 1);
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u32 rm_val = state->Reg[rm_idx];
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u32 rm_val = state->Reg[rm_idx];
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@ -6354,13 +6357,14 @@ L_stm_s_takeabort:
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state->Reg[rd_idx] = (rn_lo * rm_lo) - (rn_hi * rm_hi);
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state->Reg[rd_idx] = (rn_lo * rm_lo) - (rn_hi * rm_hi);
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}
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}
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// SMLAD
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// SMLAD
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else {
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else if ((instr & 0xd0) == 0x10) {
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const u8 ra_idx = BITS(12, 15);
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state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi) + (s32)state->Reg[ra_idx];
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state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi) + (s32)state->Reg[ra_idx];
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}
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}
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// SMLSD
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else {
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state->Reg[rd_idx] = ((rn_lo * rm_lo) - (rn_hi * rm_hi)) + (s32)state->Reg[ra_idx];
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}
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return 1;
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return 1;
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} else {
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printf ("Unhandled v6 insn: smlsd\n");
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}
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}
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break;
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break;
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case 0x74:
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case 0x74:
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