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Merge pull request #669 from lioncash/cruft
armmmu: Remove unnecessary enum values
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commit
5ac2a41f72
@ -26,36 +26,26 @@
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// Register numbers in the MMU
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enum
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{
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MMU_ID = 0,
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MMU_CONTROL = 1,
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MMU_TRANSLATION_TABLE_BASE = 2,
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MMU_DOMAIN_ACCESS_CONTROL = 3,
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MMU_FAULT_STATUS = 5,
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MMU_FAULT_ADDRESS = 6,
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MMU_CACHE_OPS = 7,
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MMU_TLB_OPS = 8,
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MMU_CACHE_LOCKDOWN = 9,
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MMU_TLB_LOCKDOWN = 10,
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MMU_PID = 13,
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MMU_ID = 0,
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MMU_CONTROL = 1,
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MMU_TRANSLATION_TABLE_BASE = 2,
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MMU_DOMAIN_ACCESS_CONTROL = 3,
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MMU_FAULT_STATUS = 5,
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MMU_FAULT_ADDRESS = 6,
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MMU_CACHE_OPS = 7,
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MMU_TLB_OPS = 8,
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MMU_CACHE_LOCKDOWN = 9,
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MMU_TLB_LOCKDOWN = 10,
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MMU_PID = 13,
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// MMU_V4
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MMU_V4_CACHE_OPS = 7,
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MMU_V4_TLB_OPS = 8,
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// MMU_V4
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MMU_V4_CACHE_OPS = 7,
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MMU_V4_TLB_OPS = 8,
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// MMU_V3
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MMU_V3_FLUSH_TLB = 5,
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MMU_V3_FLUSH_TLB_ENTRY = 6,
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MMU_V3_FLUSH_CACHE = 7,
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// MMU Intel SA-1100
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MMU_SA_RB_OPS = 9,
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MMU_SA_DEBUG = 14,
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MMU_SA_CP15_R15 = 15,
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// Intel xscale CP15
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XSCALE_CP15_CACHE_TYPE = 0,
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XSCALE_CP15_AUX_CONTROL = 1,
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XSCALE_CP15_COPRO_ACCESS = 15,
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// MMU_V3
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MMU_V3_FLUSH_TLB = 5,
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MMU_V3_FLUSH_TLB_ENTRY = 6,
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MMU_V3_FLUSH_CACHE = 7,
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};
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// Reads data in big/little endian format based on the
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