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Disassembler: ARMv6K hint instructions
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@ -4,6 +4,7 @@
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#include "common/string_util.h"
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#include "core/arm/disassembler/arm_disasm.h"
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#include "core/arm/skyeye_common/armsupp.h"
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static const char *cond_names[] = {
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"eq",
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@ -58,11 +59,13 @@ static const char *opcode_names[] = {
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"msr",
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"mul",
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"mvn",
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"nop",
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"orr",
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"pld",
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"rsb",
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"rsc",
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"sbc",
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"sev",
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"smlal",
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"smull",
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"stc",
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@ -80,6 +83,9 @@ static const char *opcode_names[] = {
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"tst",
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"umlal",
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"umull",
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"wfe",
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"wfi",
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"yield",
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"undefined",
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"adc",
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@ -204,6 +210,12 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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return DisassembleMSR(insn);
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case OP_MUL:
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return DisassembleMUL(opcode, insn);
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case OP_NOP:
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case OP_SEV:
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case OP_WFE:
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case OP_WFI:
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case OP_YIELD:
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return DisassembleNoOperands(opcode, insn);
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case OP_PLD:
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return DisassemblePLD(insn);
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case OP_STC:
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@ -646,6 +658,12 @@ std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
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cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm);
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}
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std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, uint32_t insn)
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{
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uint32_t cond = BITS(insn, 28, 31);
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return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
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}
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std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
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{
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uint8_t is_reg = (insn >> 25) & 0x1;
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@ -739,6 +757,12 @@ Opcode ARM_Disasm::Decode00(uint32_t insn) {
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}
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}
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uint32_t op1 = BITS(insn, 20, 24);
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if (bit25 && (op1 == 0x12 || op1 == 0x16)) {
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// One of the MSR (immediate) and hints instructions
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return DecodeMSRImmAndHints(insn);
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}
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// One of the data processing instructions
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return DecodeALU(insn);
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}
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@ -878,6 +902,31 @@ Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
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return OP_SMLAL;
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}
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Opcode ARM_Disasm::DecodeMSRImmAndHints(uint32_t insn) {
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uint32_t op = BIT(insn, 22);
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uint32_t op1 = BITS(insn, 16, 19);
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uint32_t op2 = BITS(insn, 0, 7);
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if (op == 0 && op1 == 0) {
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switch (op2) {
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case 0x0:
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return OP_NOP;
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case 0x1:
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return OP_YIELD;
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case 0x2:
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return OP_WFE;
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case 0x3:
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return OP_WFI;
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case 0x4:
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return OP_SEV;
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default:
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return OP_UNDEFINED;
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}
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}
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return OP_MSR;
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}
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Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t bits_65 = (insn >> 5) & 0x3;
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@ -41,11 +41,13 @@ enum Opcode {
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OP_MSR,
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OP_MUL,
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OP_MVN,
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OP_NOP,
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OP_ORR,
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OP_PLD,
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OP_RSB,
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OP_RSC,
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OP_SBC,
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OP_SEV,
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OP_SMLAL,
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OP_SMULL,
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OP_STC,
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@ -63,6 +65,9 @@ enum Opcode {
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OP_TST,
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OP_UMLAL,
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OP_UMULL,
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OP_WFE,
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OP_WFI,
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OP_YIELD,
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// Define thumb opcodes
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OP_THUMB_UNDEFINED,
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@ -118,6 +123,7 @@ class ARM_Disasm {
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static Opcode Decode10(uint32_t insn);
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static Opcode Decode11(uint32_t insn);
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static Opcode DecodeMUL(uint32_t insn);
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static Opcode DecodeMSRImmAndHints(uint32_t insn);
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static Opcode DecodeLDRH(uint32_t insn);
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static Opcode DecodeALU(uint32_t insn);
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@ -135,6 +141,7 @@ class ARM_Disasm {
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static std::string DisassembleMUL(Opcode opcode, uint32_t insn);
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static std::string DisassembleMRS(uint32_t insn);
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static std::string DisassembleMSR(uint32_t insn);
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static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
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static std::string DisassemblePLD(uint32_t insn);
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static std::string DisassembleSWI(uint32_t insn);
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static std::string DisassembleSWP(Opcode opcode, uint32_t insn);
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