ARM_Interface: Allow for partial invalidation of instruction cache

This commit is contained in:
MerryMage 2017-09-11 12:54:14 +01:00
parent cdde8ddb04
commit 647e553f64
5 changed files with 18 additions and 0 deletions

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@ -4,6 +4,7 @@
#pragma once
#include <cstddef>
#include "common/common_types.h"
#include "core/arm/skyeye_common/arm_regformat.h"
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
@ -33,6 +34,13 @@ public:
/// Clear all instruction cache
virtual void ClearInstructionCache() = 0;
/**
* Invalidate the code cache at a range of addresses.
* @param start_address The starting address of the range to invalidate.
* @param length The length (in bytes) of the range to invalidate.
*/
virtual void InvalidateCacheRange(u32 start_address, size_t length) = 0;
/// Notify CPU emulation that page tables have changed
virtual void PageTableChanged() = 0;

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@ -187,6 +187,10 @@ void ARM_Dynarmic::ClearInstructionCache() {
}
}
void ARM_Dynarmic::InvalidateCacheRange(u32 start_address, size_t length) {
jit->InvalidateCacheRange(start_address, length);
}
void ARM_Dynarmic::PageTableChanged() {
current_page_table = Memory::GetCurrentPageTable();

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@ -41,6 +41,7 @@ public:
void PrepareReschedule() override;
void ClearInstructionCache() override;
void InvalidateCacheRange(u32 start_address, size_t length) override;
void PageTableChanged() override;
private:

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@ -34,6 +34,10 @@ void ARM_DynCom::ClearInstructionCache() {
trans_cache_buf_top = 0;
}
void ARM_DynCom::InvalidateCacheRange(u32, size_t) {
ClearInstructionCache();
}
void ARM_DynCom::PageTableChanged() {
ClearInstructionCache();
}

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@ -19,6 +19,7 @@ public:
void Step() override;
void ClearInstructionCache() override;
void InvalidateCacheRange(u32 start_address, size_t length) override;
void PageTableChanged() override;
void SetPC(u32 pc) override;