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Merge pull request #1618 from MerryMage/one-step
Prevent cache overflow when single stepping
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commit
80c16961ae
@ -36,7 +36,8 @@ enum {
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CALL = (1 << 4),
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CALL = (1 << 4),
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RET = (1 << 5),
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RET = (1 << 5),
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END_OF_PAGE = (1 << 6),
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END_OF_PAGE = (1 << 6),
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THUMB = (1 << 7)
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THUMB = (1 << 7),
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SINGLE_STEP = (1 << 8)
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};
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};
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#define RM BITS(sht_oper, 0, 3)
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#define RM BITS(sht_oper, 0, 3)
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@ -3466,7 +3467,35 @@ enum {
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MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
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MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
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static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
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static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr, ARM_INST_PTR& inst_base) {
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unsigned int inst_size = 4;
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unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
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// If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction
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if (cpu->TFlag) {
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u32 arm_inst;
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ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
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// We have translated the Thumb branch instruction in the Thumb decoder
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if (state == ThumbDecodeStatus::BRANCH) {
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return inst_size;
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}
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inst = arm_inst;
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}
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int idx;
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if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
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std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
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LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst);
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LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
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CITRA_IGNORE_EXIT(-1);
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}
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inst_base = arm_instruction_trans[idx](inst, idx);
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return inst_size;
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}
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static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr) {
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Common::Profiling::ScopeTimer timer_decode(profile_decode);
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Common::Profiling::ScopeTimer timer_decode(profile_decode);
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MICROPROFILE_SCOPE(DynCom_Decode);
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MICROPROFILE_SCOPE(DynCom_Decode);
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@ -3475,8 +3504,6 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
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// Go on next, until terminal instruction
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// Go on next, until terminal instruction
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// Save start addr of basicblock in CreamCache
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// Save start addr of basicblock in CreamCache
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ARM_INST_PTR inst_base = nullptr;
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ARM_INST_PTR inst_base = nullptr;
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unsigned int inst, inst_size = 4;
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int idx;
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int ret = NON_BRANCH;
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int ret = NON_BRANCH;
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int size = 0; // instruction size of basic block
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int size = 0; // instruction size of basic block
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bb_start = top;
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bb_start = top;
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@ -3485,30 +3512,10 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
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u32 pc_start = cpu->Reg[15];
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u32 pc_start = cpu->Reg[15];
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while (ret == NON_BRANCH) {
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while (ret == NON_BRANCH) {
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inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
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unsigned int inst_size = InterpreterTranslateInstruction(cpu, phys_addr, inst_base);
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size++;
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size++;
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// If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction
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if (cpu->TFlag) {
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u32 arm_inst;
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ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
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// We have translated the Thumb branch instruction in the Thumb decoder
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if (state == ThumbDecodeStatus::BRANCH) {
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goto translated;
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}
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inst = arm_inst;
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}
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if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
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std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
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LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst);
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LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
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CITRA_IGNORE_EXIT(-1);
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}
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inst_base = arm_instruction_trans[idx](inst, idx);
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translated:
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phys_addr += inst_size;
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phys_addr += inst_size;
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if ((phys_addr & 0xfff) == 0) {
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if ((phys_addr & 0xfff) == 0) {
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@ -3522,6 +3529,27 @@ translated:
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return KEEP_GOING;
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return KEEP_GOING;
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}
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}
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static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr) {
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Common::Profiling::ScopeTimer timer_decode(profile_decode);
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MICROPROFILE_SCOPE(DynCom_Decode);
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ARM_INST_PTR inst_base = nullptr;
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bb_start = top;
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u32 phys_addr = addr;
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u32 pc_start = cpu->Reg[15];
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InterpreterTranslateInstruction(cpu, phys_addr, inst_base);
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if (inst_base->br == NON_BRANCH) {
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inst_base->br = SINGLE_STEP;
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}
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cpu->instruction_cache[pc_start] = bb_start;
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return KEEP_GOING;
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}
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static int clz(unsigned int x) {
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static int clz(unsigned int x) {
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int n;
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int n;
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if (x == 0) return (32);
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if (x == 0) return (32);
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@ -3871,8 +3899,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
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auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
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if (itr != cpu->instruction_cache.end()) {
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if (itr != cpu->instruction_cache.end()) {
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ptr = itr->second;
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ptr = itr->second;
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} else if (cpu->NumInstrsToExecute != 1) {
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if (InterpreterTranslateBlock(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
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goto END;
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} else {
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} else {
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if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
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if (InterpreterTranslateSingle(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
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goto END;
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goto END;
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}
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}
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