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armemu: Implement UHADD8, UHADD16, UHSUB8, UHSUB16, UHASX, and UHSAX
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e5ddbfee02
commit
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@ -6139,8 +6139,79 @@ L_stm_s_takeabort:
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printf ("Unhandled v6 insn: uqsub16\n");
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}
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break;
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case 0x67:
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printf ("Unhandled v6 insn: uhadd/uhsub\n");
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case 0x67: // UHADD16, UHASX, UHSAX, UHSUB16, UHADD8, and UHSUB8.
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{
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const u8 op2 = BITS(5, 7);
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const u8 rm_idx = BITS(0, 3);
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const u8 rn_idx = BITS(16, 19);
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const u8 rd_idx = BITS(12, 15);
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const u32 rm_val = state->Reg[rm_idx];
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const u32 rn_val = state->Reg[rn_idx];
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if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03)
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{
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u32 lo_val = 0;
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u32 hi_val = 0;
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// UHADD16
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if (op2 == 0x00) {
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lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF);
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hi_val = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
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}
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// UHASX
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else if (op2 == 0x01) {
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lo_val = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
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hi_val = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF);
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}
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// UHSAX
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else if (op2 == 0x02) {
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lo_val = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
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hi_val = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF);
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}
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// UHSUB16
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else if (op2 == 0x03) {
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lo_val = (rn_val & 0xFFFF) - (rm_val & 0xFFFF);
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hi_val = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
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}
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lo_val >>= 1;
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hi_val >>= 1;
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state->Reg[rd_idx] = (lo_val & 0xFFFF) | ((hi_val & 0xFFFF) << 16);
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return 1;
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}
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else if (op2 == 0x04 || op2 == 0x07) {
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u32 sum1;
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u32 sum2;
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u32 sum3;
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u32 sum4;
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// UHADD8
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if (op2 == 0x04) {
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sum1 = (rn_val & 0xFF) + (rm_val & 0xFF);
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sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF);
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sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF);
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sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF);
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}
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// UHSUB8
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else {
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sum1 = (rn_val & 0xFF) - (rm_val & 0xFF);
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sum2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF);
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sum3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF);
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sum4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF);
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}
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sum1 >>= 1;
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sum2 >>= 1;
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sum3 >>= 1;
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sum4 >>= 1;
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state->Reg[rd_idx] = (sum1 & 0xFF) | ((sum2 & 0xFF) << 8) | ((sum3 & 0xFF) << 16) | ((sum4 & 0xFF) << 24);
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return 1;
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}
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}
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break;
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case 0x68:
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{
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