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dyncom: Move over QADD16/QASX/QSAX/QSUB16
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@ -2390,15 +2390,41 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index)
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return inst_base;
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return inst_base;
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}
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADDSUBX"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->op1 = BITS(inst, 20, 21);
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inst_cream->op2 = BITS(inst, 5, 7);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUBADDX"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd16)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index)
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{
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst));
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst));
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@ -5561,15 +5587,69 @@ unsigned InterpreterMainLoop(ARMul_State* state)
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GOTO_NEXT_INST;
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GOTO_NEXT_INST;
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}
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}
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QADD_INST:
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QADD_INST:
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QADD16_INST:
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QADD8_INST:
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QADD8_INST:
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QADD16_INST:
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QADDSUBX_INST:
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QADDSUBX_INST:
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QSUB16_INST:
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QSUBADDX_INST:
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{
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INC_ICOUNTER;
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const s16 rm_lo = (RM & 0xFFFF);
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const s16 rm_hi = ((RM >> 16) & 0xFFFF);
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const s16 rn_lo = (RN & 0xFFFF);
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const s16 rn_hi = ((RN >> 16) & 0xFFFF);
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const u8 op2 = inst_cream->op2;
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s32 lo_result = 0;
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s32 hi_result = 0;
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// QADD16
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if (op2 == 0x00) {
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lo_result = (rn_lo + rm_lo);
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hi_result = (rn_hi + rm_hi);
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}
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// QASX
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else if (op2 == 0x01) {
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lo_result = (rn_lo - rm_hi);
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hi_result = (rn_hi + rm_lo);
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}
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// QSAX
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else if (op2 == 0x02) {
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lo_result = (rn_lo + rm_hi);
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hi_result = (rn_hi - rm_lo);
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}
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// QSUB16
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else if (op2 == 0x03) {
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lo_result = (rn_lo - rm_lo);
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hi_result = (rn_hi - rm_hi);
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}
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if (lo_result > 0x7FFF)
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lo_result = 0x7FFF;
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else if (lo_result < -0x8000)
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lo_result = -0x8000;
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if (hi_result > 0x7FFF)
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hi_result = 0x7FFF;
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else if (hi_result < -0x8000)
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hi_result = -0x8000;
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RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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QDADD_INST:
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QDADD_INST:
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QDSUB_INST:
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QDSUB_INST:
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QSUB_INST:
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QSUB_INST:
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QSUB16_INST:
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QSUB8_INST:
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QSUB8_INST:
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QSUBADDX_INST:
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REV_INST:
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REV_INST:
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{
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{
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INC_ICOUNTER;
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INC_ICOUNTER;
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