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dyncom: Migrate exclusive memory access control into armstate
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db4e99c186
commit
a507ea23c1
@ -47,27 +47,6 @@ enum {
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typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
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typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
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// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
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// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
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// support LDR/STREXD.
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static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
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// Exclusive memory access
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static int exclusive_detect(ARMul_State* state, u32 addr) {
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if(state->exclusive_tag == (addr & RESERVATION_GRANULE_MASK))
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return 0;
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else
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return -1;
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}
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static void add_exclusive_addr(ARMul_State* state, u32 addr){
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state->exclusive_tag = addr & RESERVATION_GRANULE_MASK;
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}
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static void remove_exclusive(ARMul_State* state, u32 addr){
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state->exclusive_tag = 0xFFFFFFFF;
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}
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static int CondPassed(ARMul_State* cpu, unsigned int cond) {
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static int CondPassed(ARMul_State* cpu, unsigned int cond) {
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const u32 NFLAG = cpu->NFlag;
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const u32 NFLAG = cpu->NFlag;
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const u32 ZFLAG = cpu->ZFlag;
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const u32 ZFLAG = cpu->ZFlag;
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@ -4170,9 +4149,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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CLREX_INST:
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CLREX_INST:
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{
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{
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remove_exclusive(cpu, 0);
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cpu->UnsetExclusiveMemoryAddress();
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cpu->exclusive_state = 0;
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cpu->Reg[15] += cpu->GetInstructionSize();
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cpu->Reg[15] += cpu->GetInstructionSize();
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INC_PC(sizeof(clrex_inst));
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INC_PC(sizeof(clrex_inst));
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FETCH_INST;
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FETCH_INST;
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@ -4539,8 +4516,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int read_addr = RN;
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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cpu->SetExclusiveMemoryAddress(read_addr);
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cpu->exclusive_state = 1;
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RD = cpu->ReadMemory32(read_addr);
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RD = cpu->ReadMemory32(read_addr);
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if (inst_cream->Rd == 15) {
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if (inst_cream->Rd == 15) {
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@ -4559,8 +4535,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int read_addr = RN;
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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cpu->SetExclusiveMemoryAddress(read_addr);
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cpu->exclusive_state = 1;
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RD = Memory::Read8(read_addr);
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RD = Memory::Read8(read_addr);
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if (inst_cream->Rd == 15) {
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if (inst_cream->Rd == 15) {
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@ -4579,8 +4554,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int read_addr = RN;
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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cpu->SetExclusiveMemoryAddress(read_addr);
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cpu->exclusive_state = 1;
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RD = cpu->ReadMemory16(read_addr);
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RD = cpu->ReadMemory16(read_addr);
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if (inst_cream->Rd == 15) {
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if (inst_cream->Rd == 15) {
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@ -4599,8 +4573,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int read_addr = RN;
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unsigned int read_addr = RN;
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add_exclusive_addr(cpu, read_addr);
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cpu->SetExclusiveMemoryAddress(read_addr);
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cpu->exclusive_state = 1;
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RD = cpu->ReadMemory32(read_addr);
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RD = cpu->ReadMemory32(read_addr);
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RD2 = cpu->ReadMemory32(read_addr + 4);
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RD2 = cpu->ReadMemory32(read_addr + 4);
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@ -6085,10 +6058,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
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if (cpu->IsExclusiveMemoryAccess(write_addr)) {
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remove_exclusive(cpu, write_addr);
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cpu->UnsetExclusiveMemoryAddress();
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cpu->exclusive_state = 0;
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cpu->WriteMemory32(write_addr, RM);
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cpu->WriteMemory32(write_addr, RM);
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RD = 0;
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RD = 0;
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} else {
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} else {
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@ -6107,10 +6078,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
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if (cpu->IsExclusiveMemoryAccess(write_addr)) {
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remove_exclusive(cpu, write_addr);
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cpu->UnsetExclusiveMemoryAddress();
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cpu->exclusive_state = 0;
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Memory::Write8(write_addr, cpu->Reg[inst_cream->Rm]);
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Memory::Write8(write_addr, cpu->Reg[inst_cream->Rm]);
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RD = 0;
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RD = 0;
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} else {
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} else {
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@ -6129,9 +6098,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
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if (cpu->IsExclusiveMemoryAccess(write_addr)) {
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remove_exclusive(cpu, write_addr);
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cpu->UnsetExclusiveMemoryAddress();
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cpu->exclusive_state = 0;
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const u32 rt = cpu->Reg[inst_cream->Rm + 0];
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const u32 rt = cpu->Reg[inst_cream->Rm + 0];
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const u32 rt2 = cpu->Reg[inst_cream->Rm + 1];
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const u32 rt2 = cpu->Reg[inst_cream->Rm + 1];
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@ -6161,10 +6129,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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unsigned int write_addr = cpu->Reg[inst_cream->Rn];
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if ((exclusive_detect(cpu, write_addr) == 0) && (cpu->exclusive_state == 1)) {
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if (cpu->IsExclusiveMemoryAccess(write_addr)) {
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remove_exclusive(cpu, write_addr);
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cpu->UnsetExclusiveMemoryAddress();
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cpu->exclusive_state = 0;
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cpu->WriteMemory16(write_addr, RM);
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cpu->WriteMemory16(write_addr, RM);
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RD = 0;
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RD = 0;
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} else {
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} else {
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@ -163,6 +163,19 @@ public:
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u32 ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const;
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u32 ReadCP15Register(u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) const;
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void WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
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void WriteCP15Register(u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
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// Exclusive memory access functions
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bool IsExclusiveMemoryAccess(u32 address) const {
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return exclusive_state && exclusive_tag == (address & RESERVATION_GRANULE_MASK);
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}
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void SetExclusiveMemoryAddress(u32 address) {
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exclusive_tag = address & RESERVATION_GRANULE_MASK;
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exclusive_state = true;
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}
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void UnsetExclusiveMemoryAddress() {
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exclusive_tag = 0xFFFFFFFF;
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exclusive_state = false;
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}
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// Whether or not the given CPU is in big endian mode (E bit is set)
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// Whether or not the given CPU is in big endian mode (E bit is set)
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bool InBigEndianMode() const {
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bool InBigEndianMode() const {
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return (Cpsr & (1 << 9)) != 0;
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return (Cpsr & (1 << 9)) != 0;
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@ -203,9 +216,6 @@ public:
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u32 Mode; // The current mode
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u32 Mode; // The current mode
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u32 Bank; // The current register bank
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u32 Bank; // The current register bank
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u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode
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u32 exclusive_state;
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u32 exclusive_result;
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u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
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u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
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unsigned int shifter_carry_out;
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unsigned int shifter_carry_out;
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@ -230,4 +240,13 @@ public:
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private:
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private:
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void ResetMPCoreCP15Registers();
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void ResetMPCoreCP15Registers();
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// Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.
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// This is the smallest granule allowed by the v7 spec, and is coincidentally just large enough to
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// support LDR/STREXD.
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static const u32 RESERVATION_GRANULE_MASK = 0xFFFFFFF8;
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u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode
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u32 exclusive_result;
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bool exclusive_state;
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};
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};
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