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Implemented WriteHWRegsWithMask for GSP.
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@ -48,20 +48,42 @@ static inline InterruptRelayQueue* GetInterruptRelayQueue(u32 thread_id) {
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return reinterpret_cast<InterruptRelayQueue*>(ptr.ValueOr(nullptr));
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return reinterpret_cast<InterruptRelayQueue*>(ptr.ValueOr(nullptr));
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}
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}
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static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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/**
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* Checks if the parameters in a register write call are valid and logs in the case that
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* they are not
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* @param base_address The first address in the sequence of registers that will be written
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* @param size_in_bytes The number of registers that will be written
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* @return true if the parameters are valid, false otherwise
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*/
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static bool CheckWriteParameters(u32 base_address, u32 size_in_bytes) {
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// TODO: Return proper error codes
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// TODO: Return proper error codes
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if (base_address + size_in_bytes >= 0x420000) {
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if (base_address + size_in_bytes >= 0x420000) {
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LOG_ERROR(Service_GSP, "Write address out of range! (address=0x%08x, size=0x%08x)",
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LOG_ERROR(Service_GSP, "Write address out of range! (address=0x%08x, size=0x%08x)",
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base_address, size_in_bytes);
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base_address, size_in_bytes);
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return;
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return false;
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}
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}
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// size should be word-aligned
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// size should be word-aligned
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if ((size_in_bytes % 4) != 0) {
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if ((size_in_bytes % 4) != 0) {
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LOG_ERROR(Service_GSP, "Invalid size 0x%08x", size_in_bytes);
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LOG_ERROR(Service_GSP, "Invalid size 0x%08x", size_in_bytes);
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return;
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return false;
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}
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}
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return true;
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}
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/**
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* Writes sequential GSP GPU hardware registers using an array of source data
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*
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* @param base_address The address of the first register in the sequence
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* @param size_in_bytes The number of registers to update (size of data)
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* @param data A pointer to the source data
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*/
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static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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// TODO: Return proper error codes
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if (!CheckWriteParameters(base_address, size_in_bytes))
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return;
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while (size_in_bytes > 0) {
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while (size_in_bytes > 0) {
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GPU::Write<u32>(base_address + 0x1EB00000, *data);
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GPU::Write<u32>(base_address + 0x1EB00000, *data);
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@ -71,17 +93,80 @@ static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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}
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}
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}
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}
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/// Write a GSP GPU hardware register
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/**
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* GSP_GPU::WriteHWRegs service function
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*
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* Writes sequential GSP GPU hardware registers
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*
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* Inputs:
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* 1 : address of first GPU register
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* 2 : number of registers to write sequentially
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* 4 : pointer to source data array
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*/
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static void WriteHWRegs(Service::Interface* self) {
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static void WriteHWRegs(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32 size = cmd_buff[2];
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u32* src = (u32*)Memory::GetPointer(cmd_buff[0x4]);
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u32* src = (u32*)Memory::GetPointer(cmd_buff[4]);
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WriteHWRegs(reg_addr, size, src);
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WriteHWRegs(reg_addr, size, src);
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}
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}
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/**
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* Updates sequential GSP GPU hardware registers using parallel arrays of source data and masks.
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* For each register, the value is updated only where the mask is high
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*
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* @param base_address The address of the first register in the sequence
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* @param size_in_bytes The number of registers to update (size of data)
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* @param data A pointer to the source data to use for updates
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* @param masks A pointer to the masks
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*/
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static void WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32* data, const u32* masks) {
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// TODO: Return proper error codes
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if (!CheckWriteParameters(base_address, size_in_bytes))
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return;
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while (size_in_bytes > 0) {
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const u32 reg_address = base_address + 0x1EB00000;
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u32 reg_value;
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GPU::Read<u32>(reg_value, reg_address);
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// Update the current value of the register only for set mask bits
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reg_value = (reg_value & ~*masks) | (*data | *masks);
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GPU::Write<u32>(reg_address, reg_value);
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size_in_bytes -= 4;
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++data;
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++masks;
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base_address += 4;
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}
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}
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/**
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* GSP_GPU::WriteHWRegsWithMask service function
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*
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* Updates sequential GSP GPU hardware registers using masks
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*
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* Inputs:
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* 1 : address of first GPU register
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* 2 : number of registers to update sequentially
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* 4 : pointer to source data array
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* 6 : pointer to mask array
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*/
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static void WriteHWRegsWithMask(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32* src_data = (u32*)Memory::GetPointer(cmd_buff[4]);
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u32* mask_data = (u32*)Memory::GetPointer(cmd_buff[6]);
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WriteHWRegsWithMask(reg_addr, size, src_data, mask_data);
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}
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/// Read a GSP GPU hardware register
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/// Read a GSP GPU hardware register
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static void ReadHWRegs(Service::Interface* self) {
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static void ReadHWRegs(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32* cmd_buff = Kernel::GetCommandBuffer();
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@ -350,7 +435,7 @@ static void TriggerCmdReqQueue(Service::Interface* self) {
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const Interface::FunctionInfo FunctionTable[] = {
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const Interface::FunctionInfo FunctionTable[] = {
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{0x00010082, WriteHWRegs, "WriteHWRegs"},
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{0x00010082, WriteHWRegs, "WriteHWRegs"},
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{0x00020084, nullptr, "WriteHWRegsWithMask"},
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{0x00020084, WriteHWRegsWithMask, "WriteHWRegsWithMask"},
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{0x00030082, nullptr, "WriteHWRegRepeat"},
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{0x00030082, nullptr, "WriteHWRegRepeat"},
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{0x00040080, ReadHWRegs, "ReadHWRegs"},
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{0x00040080, ReadHWRegs, "ReadHWRegs"},
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{0x00050200, SetBufferSwap, "SetBufferSwap"},
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{0x00050200, SetBufferSwap, "SetBufferSwap"},
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