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dyncom: Implement SRS
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cde671795c
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@ -2585,7 +2585,23 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index)
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inst_base->load_r15 = 1;
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); }
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static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
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ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
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inst_base->cond = AL;
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->inst = inst;
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inst_cream->get_addr = get_calc_addr_op(inst);
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst));
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@ -5963,6 +5979,21 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SRS_INST:
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{
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// SRS is unconditional
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ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
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u32 address = 0;
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inst_cream->get_addr(cpu, inst_cream->inst, address, 1);
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WriteMemory32(cpu, address + 0, cpu->Reg[14]);
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WriteMemory32(cpu, address + 4, cpu->Spsr_copy);
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ldst_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SSAT_INST:
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{
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