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Merge pull request #996 from yuriks/texture-copy
GPU: Implement TextureCopy-mode display transfers
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commit
a9fc659809
@ -418,7 +418,7 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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case CommandId::SET_DISPLAY_TRANSFER:
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{
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auto& params = command.image_copy;
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auto& params = command.display_transfer;
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
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Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
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@ -433,17 +433,22 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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// TODO: Check if texture copies are implemented correctly..
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case CommandId::SET_TEXTURE_COPY:
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{
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auto& params = command.image_copy;
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
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auto& params = command.texture_copy;
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.input_address),
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Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.output_address),
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Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.flags)), params.flags);
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.size),
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params.size);
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.input_size),
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params.in_width_gap);
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.output_size),
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params.out_width_gap);
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.flags),
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params.flags);
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// TODO: Should this register be set to 1 or should instead its value be OR-ed with 1?
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.trigger)), 1);
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// NOTE: Actual GSP ORs 1 with current register instead of overwriting. Doesn't seem to matter.
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.trigger), 1);
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break;
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}
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@ -127,7 +127,16 @@ struct Command {
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u32 in_buffer_size;
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u32 out_buffer_size;
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u32 flags;
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} image_copy;
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} display_transfer;
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struct {
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u32 in_buffer_address;
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u32 out_buffer_address;
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u32 size;
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u32 in_width_gap;
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u32 out_width_gap;
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u32 flags;
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} texture_copy;
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u8 raw_data[0x1C];
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};
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@ -3,6 +3,7 @@
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// Refer to the license.txt file included.
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#include <cstring>
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#include <numeric>
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#include <type_traits>
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#include "common/color.h"
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@ -158,14 +159,59 @@ inline void Write(u32 addr, const T data) {
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u8* src_pointer = Memory::GetPhysicalPointer(config.GetPhysicalInputAddress());
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u8* dst_pointer = Memory::GetPhysicalPointer(config.GetPhysicalOutputAddress());
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if (config.is_texture_copy) {
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u32 input_width = config.texture_copy.input_width * 16;
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u32 input_gap = config.texture_copy.input_gap * 16;
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u32 output_width = config.texture_copy.output_width * 16;
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u32 output_gap = config.texture_copy.output_gap * 16;
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size_t contiguous_input_size = config.texture_copy.size / input_width * (input_width + input_gap);
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VideoCore::g_renderer->hw_rasterizer->NotifyPreRead(config.GetPhysicalInputAddress(), contiguous_input_size);
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u32 remaining_size = config.texture_copy.size;
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u32 remaining_input = input_width;
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u32 remaining_output = output_width;
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while (remaining_size > 0) {
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u32 copy_size = std::min({ remaining_input, remaining_output, remaining_size });
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std::memcpy(dst_pointer, src_pointer, copy_size);
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src_pointer += copy_size;
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dst_pointer += copy_size;
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remaining_input -= copy_size;
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remaining_output -= copy_size;
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remaining_size -= copy_size;
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if (remaining_input == 0) {
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remaining_input = input_width;
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src_pointer += input_gap;
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}
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if (remaining_output == 0) {
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remaining_output = output_width;
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dst_pointer += output_gap;
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}
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}
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LOG_TRACE(HW_GPU, "TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> 0x%08X(%u+%u), flags 0x%08X",
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config.texture_copy.size,
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config.GetPhysicalInputAddress(), input_width, input_gap,
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config.GetPhysicalOutputAddress(), output_width, output_gap,
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config.flags);
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size_t contiguous_output_size = config.texture_copy.size / output_width * (output_width + output_gap);
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VideoCore::g_renderer->hw_rasterizer->NotifyFlush(config.GetPhysicalOutputAddress(), contiguous_output_size);
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF);
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break;
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}
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if (config.scaling > config.ScaleXY) {
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LOG_CRITICAL(HW_GPU, "Unimplemented display transfer scaling mode %u", config.scaling.Value());
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UNIMPLEMENTED();
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break;
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}
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if (config.output_tiled &&
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(config.scaling == config.ScaleXY || config.scaling == config.ScaleX)) {
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if (config.input_linear && config.scaling != config.NoScale) {
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LOG_CRITICAL(HW_GPU, "Scaling is only implemented on tiled input");
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UNIMPLEMENTED();
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break;
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@ -182,23 +228,6 @@ inline void Write(u32 addr, const T data) {
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VideoCore::g_renderer->hw_rasterizer->NotifyPreRead(config.GetPhysicalInputAddress(), input_size);
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if (config.raw_copy) {
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// Raw copies do not perform color conversion nor tiled->linear / linear->tiled conversions
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// TODO(Subv): Verify if raw copies perform scaling
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memcpy(dst_pointer, src_pointer, output_size);
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LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> 0x%08x(%ux%u), output format: %x, flags 0x%08X, Raw copy",
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output_size,
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config.GetPhysicalInputAddress(), config.input_width.Value(), config.input_height.Value(),
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config.GetPhysicalOutputAddress(), config.output_width.Value(), config.output_height.Value(),
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config.output_format.Value(), config.flags);
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF);
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VideoCore::g_renderer->hw_rasterizer->NotifyFlush(config.GetPhysicalOutputAddress(), output_size);
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break;
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}
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for (u32 y = 0; y < output_height; ++y) {
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for (u32 x = 0; x < output_width; ++x) {
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Math::Vec4<u8> src_color;
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@ -220,7 +249,7 @@ inline void Write(u32 addr, const T data) {
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u32 src_offset;
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u32 dst_offset;
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if (config.output_tiled) {
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if (config.input_linear) {
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if (!config.dont_swizzle) {
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// Interpret the input as linear and the output as tiled
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u32 coarse_y = y & ~7;
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@ -201,12 +201,14 @@ struct Regs {
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u32 flags;
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BitField< 0, 1, u32> flip_vertically; // flips input data vertically
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BitField< 1, 1, u32> output_tiled; // Converts from linear to tiled format
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BitField< 3, 1, u32> raw_copy; // Copies the data without performing any processing
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BitField< 1, 1, u32> input_linear; // Converts from linear to tiled format
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BitField< 2, 1, u32> crop_input_lines;
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BitField< 3, 1, u32> is_texture_copy; // Copies the data without performing any processing and respecting texture copy fields
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BitField< 5, 1, u32> dont_swizzle;
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BitField< 8, 3, PixelFormat> input_format;
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BitField<12, 3, PixelFormat> output_format;
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/// Uses some kind of 32x32 block swizzling mode, instead of the usual 8x8 one.
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BitField<16, 1, u32> block_32; // TODO(yuriks): unimplemented
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BitField<24, 2, ScalingMode> scaling; // Determines the scaling mode of the transfer
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};
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@ -214,10 +216,30 @@ struct Regs {
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// it seems that writing to this field triggers the display transfer
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u32 trigger;
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} display_transfer_config;
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ASSERT_MEMBER_SIZE(display_transfer_config, 0x1c);
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INSERT_PADDING_WORDS(0x331);
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INSERT_PADDING_WORDS(0x1);
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struct {
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u32 size;
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union {
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u32 input_size;
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BitField< 0, 16, u32> input_width;
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BitField<16, 16, u32> input_gap;
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};
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union {
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u32 output_size;
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BitField< 0, 16, u32> output_width;
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BitField<16, 16, u32> output_gap;
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};
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} texture_copy;
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} display_transfer_config;
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ASSERT_MEMBER_SIZE(display_transfer_config, 0x2c);
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INSERT_PADDING_WORDS(0x32D);
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struct {
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// command list size (in bytes)
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