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https://github.com/citra-mirror/citra.git
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GSP: Return proper error codes for register writes
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644fbbeb13
commit
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@ -24,6 +24,7 @@ enum class ErrorDescription : u32 {
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FS_InvalidOpenFlags = 230,
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FS_InvalidOpenFlags = 230,
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FS_NotAFile = 250,
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FS_NotAFile = 250,
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FS_NotFormatted = 340, ///< This is used by the FS service when creating a SaveData archive
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FS_NotFormatted = 340, ///< This is used by the FS service when creating a SaveData archive
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OutofRangeOrMisalignedAddress = 513, // TODO(purpasmart): Check if this name fits its actual usage
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FS_InvalidPath = 702,
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FS_InvalidPath = 702,
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InvalidSection = 1000,
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InvalidSection = 1000,
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TooLarge = 1001,
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TooLarge = 1001,
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@ -31,6 +31,13 @@ const static u32 REGS_BEGIN = 0x1EB00000;
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namespace GSP_GPU {
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namespace GSP_GPU {
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const ResultCode ERR_GSP_REGS_OUTOFRANGE_OR_MISALIGNED(ErrorDescription::OutofRangeOrMisalignedAddress, ErrorModule::GX,
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ErrorSummary::InvalidArgument, ErrorLevel::Usage); // 0xE0E02A01
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const ResultCode ERR_GSP_REGS_MISALIGNED(ErrorDescription::MisalignedSize, ErrorModule::GX,
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ErrorSummary::InvalidArgument, ErrorLevel::Usage); // 0xE0E02BF2
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const ResultCode ERR_GSP_REGS_INVALID_SIZE(ErrorDescription::InvalidSize, ErrorModule::GX,
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ErrorSummary::InvalidArgument, ErrorLevel::Usage); // 0xE0E02BEC
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/// Event triggered when GSP interrupt has been signalled
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/// Event triggered when GSP interrupt has been signalled
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Kernel::SharedPtr<Kernel::Event> g_interrupt_event;
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Kernel::SharedPtr<Kernel::Event> g_interrupt_event;
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/// GSP shared memoryings
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/// GSP shared memoryings
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@ -58,48 +65,88 @@ static inline InterruptRelayQueue* GetInterruptRelayQueue(u32 thread_id) {
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return reinterpret_cast<InterruptRelayQueue*>(ptr);
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return reinterpret_cast<InterruptRelayQueue*>(ptr);
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}
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}
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/**
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* Checks if the parameters in a register write call are valid and logs in the case that
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* they are not
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* @param base_address The first address in the sequence of registers that will be written
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* @param size_in_bytes The number of registers that will be written
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* @return true if the parameters are valid, false otherwise
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*/
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static bool CheckWriteParameters(u32 base_address, u32 size_in_bytes) {
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// TODO: Return proper error codes
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if (base_address + size_in_bytes >= 0x420000) {
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LOG_ERROR(Service_GSP, "Write address out of range! (address=0x%08x, size=0x%08x)",
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base_address, size_in_bytes);
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return false;
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}
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// size should be word-aligned
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if ((size_in_bytes % 4) != 0) {
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LOG_ERROR(Service_GSP, "Invalid size 0x%08x", size_in_bytes);
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return false;
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}
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return true;
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}
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/**
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/**
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* Writes sequential GSP GPU hardware registers using an array of source data
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* Writes sequential GSP GPU hardware registers using an array of source data
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*
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*
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* @param base_address The address of the first register in the sequence
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* @param base_address The address of the first register in the sequence
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* @param size_in_bytes The number of registers to update (size of data)
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* @param size_in_bytes The number of registers to update (size of data)
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* @param data A pointer to the source data
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* @param data A pointer to the source data
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* @return RESULT_SUCCESS if the parameters are valid, error code otherwise
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*/
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*/
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static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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static ResultCode WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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// TODO: Return proper error codes
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// This magic number is verified to be done by the gsp module
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if (!CheckWriteParameters(base_address, size_in_bytes))
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const u32 max_size_in_bytes = 0x80;
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return;
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while (size_in_bytes > 0) {
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if (base_address & 3 || base_address >= 0x420000) {
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HW::Write<u32>(base_address + REGS_BEGIN, *data);
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LOG_ERROR(Service_GSP, "Write address was out of range or misaligned! (address=0x%08x, size=0x%08x)",
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base_address, size_in_bytes);
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return ERR_GSP_REGS_OUTOFRANGE_OR_MISALIGNED;
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} else if (size_in_bytes <= max_size_in_bytes) {
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if (size_in_bytes & 3) {
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LOG_ERROR(Service_GSP, "Misaligned size 0x%08x", size_in_bytes);
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return ERR_GSP_REGS_MISALIGNED;
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} else {
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while (size_in_bytes > 0) {
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HW::Write<u32>(base_address + REGS_BEGIN, *data);
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size_in_bytes -= 4;
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size_in_bytes -= 4;
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++data;
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++data;
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base_address += 4;
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base_address += 4;
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}
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return RESULT_SUCCESS;
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}
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} else {
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LOG_ERROR(Service_GSP, "Out of range size 0x%08x", size_in_bytes);
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return ERR_GSP_REGS_INVALID_SIZE;
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}
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}
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/**
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* Updates sequential GSP GPU hardware registers using parallel arrays of source data and masks.
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* For each register, the value is updated only where the mask is high
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*
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* @param base_address The address of the first register in the sequence
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* @param size_in_bytes The number of registers to update (size of data)
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* @param data A pointer to the source data to use for updates
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* @param masks A pointer to the masks
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* @return RESULT_SUCCESS if the parameters are valid, error code otherwise
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*/
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static ResultCode WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32* data, const u32* masks) {
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// This magic number is verified to be done by the gsp module
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const u32 max_size_in_bytes = 0x80;
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if (base_address & 3 || base_address >= 0x420000) {
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LOG_ERROR(Service_GSP, "Write address was out of range or misaligned! (address=0x%08x, size=0x%08x)",
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base_address, size_in_bytes);
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return ERR_GSP_REGS_OUTOFRANGE_OR_MISALIGNED;
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} else if (size_in_bytes <= max_size_in_bytes) {
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if (size_in_bytes & 3) {
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LOG_ERROR(Service_GSP, "Misaligned size 0x%08x", size_in_bytes);
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return ERR_GSP_REGS_MISALIGNED;
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} else {
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while (size_in_bytes > 0) {
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const u32 reg_address = base_address + REGS_BEGIN;
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u32 reg_value;
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HW::Read<u32>(reg_value, reg_address);
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// Update the current value of the register only for set mask bits
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reg_value = (reg_value & ~*masks) | (*data | *masks);
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HW::Write<u32>(reg_address, reg_value);
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size_in_bytes -= 4;
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++data;
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++masks;
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base_address += 4;
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}
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return RESULT_SUCCESS;
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}
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} else {
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LOG_ERROR(Service_GSP, "Out of range size 0x%08x", size_in_bytes);
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return ERR_GSP_REGS_INVALID_SIZE;
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}
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}
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}
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}
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@ -120,39 +167,7 @@ static void WriteHWRegs(Service::Interface* self) {
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u32* src = (u32*)Memory::GetPointer(cmd_buff[4]);
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u32* src = (u32*)Memory::GetPointer(cmd_buff[4]);
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WriteHWRegs(reg_addr, size, src);
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cmd_buff[1] = WriteHWRegs(reg_addr, size, src).raw;
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}
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/**
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* Updates sequential GSP GPU hardware registers using parallel arrays of source data and masks.
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* For each register, the value is updated only where the mask is high
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*
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* @param base_address The address of the first register in the sequence
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* @param size_in_bytes The number of registers to update (size of data)
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* @param data A pointer to the source data to use for updates
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* @param masks A pointer to the masks
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*/
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static void WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32* data, const u32* masks) {
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// TODO: Return proper error codes
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if (!CheckWriteParameters(base_address, size_in_bytes))
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return;
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while (size_in_bytes > 0) {
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const u32 reg_address = base_address + REGS_BEGIN;
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u32 reg_value;
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HW::Read<u32>(reg_value, reg_address);
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// Update the current value of the register only for set mask bits
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reg_value = (reg_value & ~*masks) | (*data | *masks);
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HW::Write<u32>(reg_address, reg_value);
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size_in_bytes -= 4;
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++data;
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++masks;
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base_address += 4;
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}
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}
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}
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/**
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/**
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@ -174,7 +189,7 @@ static void WriteHWRegsWithMask(Service::Interface* self) {
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u32* src_data = (u32*)Memory::GetPointer(cmd_buff[4]);
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u32* src_data = (u32*)Memory::GetPointer(cmd_buff[4]);
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u32* mask_data = (u32*)Memory::GetPointer(cmd_buff[6]);
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u32* mask_data = (u32*)Memory::GetPointer(cmd_buff[6]);
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WriteHWRegsWithMask(reg_addr, size, src_data, mask_data);
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cmd_buff[1] = WriteHWRegsWithMask(reg_addr, size, src_data, mask_data).raw;
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}
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}
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/// Read a GSP GPU hardware register
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/// Read a GSP GPU hardware register
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@ -206,27 +221,27 @@ static void ReadHWRegs(Service::Interface* self) {
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}
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}
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}
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}
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void SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
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ResultCode SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
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u32 base_address = 0x400000;
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u32 base_address = 0x400000;
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PAddr phys_address_left = Memory::VirtualToPhysicalAddress(info.address_left);
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PAddr phys_address_left = Memory::VirtualToPhysicalAddress(info.address_left);
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PAddr phys_address_right = Memory::VirtualToPhysicalAddress(info.address_right);
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PAddr phys_address_right = Memory::VirtualToPhysicalAddress(info.address_right);
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if (info.active_fb == 0) {
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if (info.active_fb == 0) {
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)), 4,
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)),
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&phys_address_left);
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4, &phys_address_left);
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)), 4,
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)),
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&phys_address_right);
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4, &phys_address_right);
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} else {
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} else {
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)), 4,
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)),
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&phys_address_left);
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4, &phys_address_left);
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)), 4,
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)),
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&phys_address_right);
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4, &phys_address_right);
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}
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}
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)), 4,
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)),
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&info.stride);
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4, &info.stride);
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].color_format)), 4,
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].color_format)),
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&info.format);
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4, &info.format);
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)), 4,
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)),
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&info.shown_fb);
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4, &info.shown_fb);
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if (Pica::g_debug_context)
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if (Pica::g_debug_context)
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Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::BufferSwapped, nullptr);
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Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::BufferSwapped, nullptr);
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@ -234,6 +249,8 @@ void SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
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if (screen_id == 0) {
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if (screen_id == 0) {
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MicroProfileFlip();
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MicroProfileFlip();
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}
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}
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return RESULT_SUCCESS;
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}
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}
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/**
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/**
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@ -251,9 +268,8 @@ static void SetBufferSwap(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 screen_id = cmd_buff[1];
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u32 screen_id = cmd_buff[1];
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FrameBufferInfo* fb_info = (FrameBufferInfo*)&cmd_buff[2];
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FrameBufferInfo* fb_info = (FrameBufferInfo*)&cmd_buff[2];
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SetBufferSwap(screen_id, *fb_info);
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cmd_buff[1] = 0; // No error
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cmd_buff[1] = SetBufferSwap(screen_id, *fb_info).raw;
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}
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}
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/**
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/**
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@ -194,7 +194,7 @@ public:
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*/
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*/
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void SignalInterrupt(InterruptId interrupt_id);
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void SignalInterrupt(InterruptId interrupt_id);
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void SetBufferSwap(u32 screen_id, const FrameBufferInfo& info);
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ResultCode SetBufferSwap(u32 screen_id, const FrameBufferInfo& info);
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/**
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/**
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* Retrieves the framebuffer info stored in the GSP shared memory for the
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* Retrieves the framebuffer info stored in the GSP shared memory for the
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