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https://github.com/citra-mirror/citra.git
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pica: move global shader buffer state into Pica::State (#4796)
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commit
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@ -30,15 +30,6 @@
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namespace Pica::CommandProcessor {
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namespace Pica::CommandProcessor {
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static int vs_float_regs_counter = 0;
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static u32 vs_uniform_write_buffer[4];
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static int gs_float_regs_counter = 0;
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static u32 gs_uniform_write_buffer[4];
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static int default_attr_counter = 0;
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static u32 default_attr_write_buffer[3];
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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static const u32 expand_bits_to_bytes[] = {
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static const u32 expand_bits_to_bytes[] = {
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0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
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0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
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@ -161,7 +152,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX(pipeline.vs_default_attributes_setup.index):
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case PICA_REG_INDEX(pipeline.vs_default_attributes_setup.index):
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g_state.immediate.current_attribute = 0;
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g_state.immediate.current_attribute = 0;
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g_state.immediate.reset_geometry_pipeline = true;
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g_state.immediate.reset_geometry_pipeline = true;
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default_attr_counter = 0;
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g_state.default_attr_counter = 0;
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break;
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break;
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// Load default vertex input attributes
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// Load default vertex input attributes
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@ -170,14 +161,14 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[2], 0x235): {
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[2], 0x235): {
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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// it directly write the values?
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default_attr_write_buffer[default_attr_counter++] = value;
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g_state.default_attr_write_buffer[g_state.default_attr_counter++] = value;
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// Default attributes are written in a packed format such that four float24 values are
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// Default attributes are written in a packed format such that four float24 values are
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// encoded in
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// encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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// written.
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if (default_attr_counter >= 3) {
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if (g_state.default_attr_counter >= 3) {
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default_attr_counter = 0;
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g_state.default_attr_counter = 0;
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auto& setup = regs.pipeline.vs_default_attributes_setup;
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auto& setup = regs.pipeline.vs_default_attributes_setup;
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@ -189,12 +180,12 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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Common::Vec4<float24> attribute;
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Common::Vec4<float24> attribute;
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// NOTE: The destination component order indeed is "backwards"
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// NOTE: The destination component order indeed is "backwards"
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attribute.w = float24::FromRaw(default_attr_write_buffer[0] >> 8);
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attribute.w = float24::FromRaw(g_state.default_attr_write_buffer[0] >> 8);
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attribute.z = float24::FromRaw(((default_attr_write_buffer[0] & 0xFF) << 16) |
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attribute.z = float24::FromRaw(((g_state.default_attr_write_buffer[0] & 0xFF) << 16) |
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((default_attr_write_buffer[1] >> 16) & 0xFFFF));
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((g_state.default_attr_write_buffer[1] >> 16) & 0xFFFF));
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attribute.y = float24::FromRaw(((default_attr_write_buffer[1] & 0xFFFF) << 8) |
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attribute.y = float24::FromRaw(((g_state.default_attr_write_buffer[1] & 0xFFFF) << 8) |
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((default_attr_write_buffer[2] >> 24) & 0xFF));
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((g_state.default_attr_write_buffer[2] >> 24) & 0xFF));
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attribute.x = float24::FromRaw(default_attr_write_buffer[2] & 0xFFFFFF);
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attribute.x = float24::FromRaw(g_state.default_attr_write_buffer[2] & 0xFFFFFF);
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LOG_TRACE(HW_GPU, "Set default VS attribute {:x} to ({} {} {} {})", (int)setup.index,
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LOG_TRACE(HW_GPU, "Set default VS attribute {:x} to ({} {} {} {})", (int)setup.index,
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attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
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attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
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@ -459,8 +450,8 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[5], 0x296):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[5], 0x296):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[6], 0x297):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[6], 0x297):
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[7], 0x298): {
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case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[7], 0x298): {
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WriteUniformFloatReg(g_state.regs.gs, g_state.gs, gs_float_regs_counter,
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WriteUniformFloatReg(g_state.regs.gs, g_state.gs, g_state.gs_float_regs_counter,
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gs_uniform_write_buffer, value);
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g_state.gs_uniform_write_buffer, value);
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break;
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break;
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}
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}
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@ -528,8 +519,8 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[6], 0x2c7):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[6], 0x2c7):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[7], 0x2c8): {
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[7], 0x2c8): {
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// TODO (wwylele): does regs.pipeline.gs_unit_exclusive_configuration affect this?
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// TODO (wwylele): does regs.pipeline.gs_unit_exclusive_configuration affect this?
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WriteUniformFloatReg(g_state.regs.vs, g_state.vs, vs_float_regs_counter,
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WriteUniformFloatReg(g_state.regs.vs, g_state.vs, g_state.vs_float_regs_counter,
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vs_uniform_write_buffer, value);
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g_state.vs_uniform_write_buffer, value);
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break;
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break;
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}
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}
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@ -50,5 +50,11 @@ void State::Reset() {
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Zero(cmd_list);
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Zero(cmd_list);
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Zero(immediate);
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Zero(immediate);
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primitive_assembler.Reconfigure(PipelineRegs::TriangleTopology::List);
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primitive_assembler.Reconfigure(PipelineRegs::TriangleTopology::List);
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vs_float_regs_counter = 0;
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Zero(vs_uniform_write_buffer);
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gs_float_regs_counter = 0;
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Zero(gs_uniform_write_buffer);
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default_attr_counter = 0;
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Zero(default_attr_write_buffer);
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}
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}
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} // namespace Pica
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} // namespace Pica
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@ -152,6 +152,15 @@ struct State {
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// This is constructed with a dummy triangle topology
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// This is constructed with a dummy triangle topology
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PrimitiveAssembler<Shader::OutputVertex> primitive_assembler;
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PrimitiveAssembler<Shader::OutputVertex> primitive_assembler;
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int vs_float_regs_counter = 0;
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u32 vs_uniform_write_buffer[4]{};
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int gs_float_regs_counter = 0;
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u32 gs_uniform_write_buffer[4]{};
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int default_attr_counter = 0;
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u32 default_attr_write_buffer[3]{};
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};
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};
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extern State g_state; ///< Current Pica state
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extern State g_state; ///< Current Pica state
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