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added some commented out ARMulator functions
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829952834a
commit
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@ -26,6 +26,7 @@
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#include "core.h"
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#include "core.h"
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#include "mem_map.h"
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#include "mem_map.h"
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#include "arm/armdefs.h"
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#include "arm/armdefs.h"
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#include "arm/armemu.h"
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#include "arm/disassembler/arm_disasm.h"
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#include "arm/disassembler/arm_disasm.h"
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namespace Core {
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namespace Core {
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@ -54,31 +55,13 @@ void RunLoop() {
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/// Step the CPU one instruction
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/// Step the CPU one instruction
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void SingleStep() {
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void SingleStep() {
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//arm11_core_t* core = (arm11_core_t*)opaque->obj;
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ARMul_State *state = core->state;
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ARMul_State *state = core->state;
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//if (state->space.conf_obj == NULL){
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// state->space.conf_obj = core->space->conf_obj;
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// state->space.read = core->space->read;
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// state->space.write = core->space->write;
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//}
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char next_instr[255];
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disasm->disasm(state->pc, Memory::Read32(state->pc), next_instr);
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NOTICE_LOG(ARM11, "0x%08X : %s", state->pc, next_instr);
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for (int i = 0; i < 15; i++) {
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NOTICE_LOG(ARM11, "Reg[%02d] = 0x%08X", i, state->Reg[i]);
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}
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state->step++;
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state->step++;
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state->cycle++;
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state->cycle++;
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state->EndCondition = 0;
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state->EndCondition = 0;
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state->stop_simulator = 0;
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state->stop_simulator = 0;
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//state->NextInstr = RESUME; /* treat as PC change */
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state->NextInstr = RESUME; /* treat as PC change */
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state->last_pc = state->Reg[15];
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state->last_pc = state->Reg[15];
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state->Reg[15] = ARMul_DoInstr(state);
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state->Reg[15] = ARMul_DoInstr(state);
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state->Cpsr = (state->Cpsr & 0x0fffffdf) | \
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state->Cpsr = (state->Cpsr & 0x0fffffdf) | \
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@ -88,7 +71,7 @@ void SingleStep() {
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(state->VFlag << 28);// | \
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(state->VFlag << 28);// | \
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//(state->TFlag << 5);
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//(state->TFlag << 5);
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//FLUSHPIPE;
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FLUSHPIPE;
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}
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}
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/// Halt the core
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/// Halt the core
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