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Merge pull request #1065 from yuriks/shader-fp
Shader FP compliance fixes
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commit
c5a4025b65
@ -1021,12 +1021,20 @@ struct float24 {
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return ret;
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}
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static float24 Zero() {
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return FromFloat32(0.f);
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}
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// Not recommended for anything but logging
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float ToFloat32() const {
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return value;
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}
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float24 operator * (const float24& flt) const {
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if ((this->value == 0.f && !std::isnan(flt.value)) ||
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(flt.value == 0.f && !std::isnan(this->value)))
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// PICA gives 0 instead of NaN when multiplying by inf
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return Zero();
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return float24::FromFloat32(ToFloat32() * flt.ToFloat32());
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}
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@ -1043,7 +1051,11 @@ struct float24 {
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}
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float24& operator *= (const float24& flt) {
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value *= flt.ToFloat32();
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if ((this->value == 0.f && !std::isnan(flt.value)) ||
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(flt.value == 0.f && !std::isnan(this->value)))
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// PICA gives 0 instead of NaN when multiplying by inf
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*this = Zero();
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else value *= flt.ToFloat32();
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return *this;
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}
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@ -177,7 +177,10 @@ void RunInterpreter(UnitState<Debug>& state) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = std::max(src1[i], src2[i]);
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// NOTE: Exact form required to match NaN semantics to hardware:
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// max(0, NaN) -> NaN
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// max(NaN, 0) -> 0
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dest[i] = (src1[i] > src2[i]) ? src1[i] : src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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@ -190,7 +193,10 @@ void RunInterpreter(UnitState<Debug>& state) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = std::min(src1[i], src2[i]);
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// NOTE: Exact form required to match NaN semantics to hardware:
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// min(0, NaN) -> NaN
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// min(NaN, 0) -> 0
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dest[i] = (src1[i] < src2[i]) ? src1[i] : src2[i];
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}
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Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
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break;
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@ -115,6 +115,8 @@ static const X64Reg SRC1 = XMM1;
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static const X64Reg SRC2 = XMM2;
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/// Loaded with the third swizzled source register, otherwise can be used as a scratch register
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static const X64Reg SRC3 = XMM3;
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/// Additional scratch register
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static const X64Reg SCRATCH2 = XMM4;
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/// Constant vector of [1.0f, 1.0f, 1.0f, 1.0f], used to efficiently set a vector to one
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static const X64Reg ONE = XMM14;
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/// Constant vector of [-0.f, -0.f, -0.f, -0.f], used to efficiently negate a vector with XOR
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@ -227,8 +229,8 @@ void JitCompiler::Compile_DestEnable(Instruction instr,X64Reg src) {
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u8 mask = ((swiz.dest_mask & 1) << 3) | ((swiz.dest_mask & 8) >> 3) | ((swiz.dest_mask & 2) << 1) | ((swiz.dest_mask & 4) >> 1);
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BLENDPS(SCRATCH, R(src), mask);
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} else {
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MOVAPS(XMM4, R(src));
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UNPCKHPS(XMM4, R(SCRATCH)); // Unpack X/Y components of source and destination
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MOVAPS(SCRATCH2, R(src));
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UNPCKHPS(SCRATCH2, R(SCRATCH)); // Unpack X/Y components of source and destination
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UNPCKLPS(SCRATCH, R(src)); // Unpack Z/W components of source and destination
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// Compute selector to selectively copy source components to destination for SHUFPS instruction
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@ -236,7 +238,7 @@ void JitCompiler::Compile_DestEnable(Instruction instr,X64Reg src) {
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((swiz.DestComponentEnabled(1) ? 3 : 2) << 2) |
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((swiz.DestComponentEnabled(2) ? 0 : 1) << 4) |
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((swiz.DestComponentEnabled(3) ? 2 : 3) << 6);
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SHUFPS(SCRATCH, R(XMM4), sel);
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SHUFPS(SCRATCH, R(SCRATCH2), sel);
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}
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// Store dest back to memory
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@ -244,6 +246,19 @@ void JitCompiler::Compile_DestEnable(Instruction instr,X64Reg src) {
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}
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}
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void JitCompiler::Compile_SanitizedMul(Gen::X64Reg src1, Gen::X64Reg src2, Gen::X64Reg scratch) {
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MOVAPS(scratch, R(src1));
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CMPPS(scratch, R(src2), CMP_ORD);
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MULPS(src1, R(src2));
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MOVAPS(src2, R(src1));
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CMPPS(src2, R(src2), CMP_UNORD);
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XORPS(scratch, R(src2));
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ANDPS(src1, R(scratch));
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}
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void JitCompiler::Compile_EvaluateCondition(Instruction instr) {
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// Note: NXOR is used below to check for equality
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switch (instr.flow_control.op) {
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@ -307,10 +322,7 @@ void JitCompiler::Compile_DP3(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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if (Common::GetCPUCaps().sse4_1) {
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DPPS(SRC1, R(SRC2), 0x7f);
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} else {
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MULPS(SRC1, R(SRC2));
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Compile_SanitizedMul(SRC1, SRC2, SCRATCH);
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC2, R(SRC2), _MM_SHUFFLE(1, 1, 1, 1));
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@ -321,7 +333,6 @@ void JitCompiler::Compile_DP3(Instruction instr) {
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 0, 0, 0));
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ADDPS(SRC1, R(SRC2));
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ADDPS(SRC1, R(SRC3));
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}
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Compile_DestEnable(instr, SRC1);
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}
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@ -330,10 +341,7 @@ void JitCompiler::Compile_DP4(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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if (Common::GetCPUCaps().sse4_1) {
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DPPS(SRC1, R(SRC2), 0xff);
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} else {
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MULPS(SRC1, R(SRC2));
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Compile_SanitizedMul(SRC1, SRC2, SCRATCH);
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(2, 3, 0, 1)); // XYZW -> ZWXY
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@ -342,7 +350,6 @@ void JitCompiler::Compile_DP4(Instruction instr) {
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3)); // XYZW -> WZYX
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ADDPS(SRC1, R(SRC2));
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}
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Compile_DestEnable(instr, SRC1);
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}
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@ -359,14 +366,14 @@ void JitCompiler::Compile_DPH(Instruction instr) {
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if (Common::GetCPUCaps().sse4_1) {
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// Set 4th component to 1.0
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BLENDPS(SRC1, R(ONE), 0x8); // 0b1000
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DPPS(SRC1, R(SRC2), 0xff);
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} else {
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// Reverse to set the 4th component to 1.0
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3));
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MOVSS(SRC1, R(ONE));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3));
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// Set 4th component to 1.0
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MOVAPS(SCRATCH, R(SRC1));
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UNPCKHPS(SCRATCH, R(ONE)); // XYZW, 1111 -> Z1__
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UNPCKLPD(SRC1, R(SCRATCH)); // XYZW, Z1__ -> XYZ1
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}
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MULPS(SRC1, R(SRC2));
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Compile_SanitizedMul(SRC1, SRC2, SCRATCH);
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(2, 3, 0, 1)); // XYZW -> ZWXY
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@ -375,7 +382,6 @@ void JitCompiler::Compile_DPH(Instruction instr) {
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3)); // XYZW -> WZYX
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ADDPS(SRC1, R(SRC2));
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}
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Compile_DestEnable(instr, SRC1);
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}
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@ -415,7 +421,7 @@ void JitCompiler::Compile_LG2(Instruction instr) {
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void JitCompiler::Compile_MUL(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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MULPS(SRC1, R(SRC2));
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Compile_SanitizedMul(SRC1, SRC2, SCRATCH);
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Compile_DestEnable(instr, SRC1);
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}
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@ -465,6 +471,7 @@ void JitCompiler::Compile_FLR(Instruction instr) {
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void JitCompiler::Compile_MAX(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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// SSE semantics match PICA200 ones: In case of NaN, SRC2 is returned.
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MAXPS(SRC1, R(SRC2));
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Compile_DestEnable(instr, SRC1);
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}
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@ -472,6 +479,7 @@ void JitCompiler::Compile_MAX(Instruction instr) {
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void JitCompiler::Compile_MIN(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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// SSE semantics match PICA200 ones: In case of NaN, SRC2 is returned.
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MINPS(SRC1, R(SRC2));
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Compile_DestEnable(instr, SRC1);
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}
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@ -578,27 +586,42 @@ void JitCompiler::Compile_CALLU(Instruction instr) {
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}
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void JitCompiler::Compile_CMP(Instruction instr) {
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using Op = Instruction::Common::CompareOpType::Op;
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Op op_x = instr.common.compare_op.x;
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Op op_y = instr.common.compare_op.y;
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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static const u8 cmp[] = { CMP_EQ, CMP_NEQ, CMP_LT, CMP_LE, CMP_NLE, CMP_NLT };
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// SSE doesn't have greater-than (GT) or greater-equal (GE) comparison operators. You need to
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// emulate them by swapping the lhs and rhs and using LT and LE. NLT and NLE can't be used here
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// because they don't match when used with NaNs.
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static const u8 cmp[] = { CMP_EQ, CMP_NEQ, CMP_LT, CMP_LE, CMP_LT, CMP_LE };
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if (instr.common.compare_op.x == instr.common.compare_op.y) {
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bool invert_op_x = (op_x == Op::GreaterThan || op_x == Op::GreaterEqual);
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Gen::X64Reg lhs_x = invert_op_x ? SRC2 : SRC1;
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Gen::X64Reg rhs_x = invert_op_x ? SRC1 : SRC2;
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if (op_x == op_y) {
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// Compare X-component and Y-component together
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CMPPS(SRC1, R(SRC2), cmp[instr.common.compare_op.x]);
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CMPPS(lhs_x, R(rhs_x), cmp[op_x]);
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MOVQ_xmm(R(COND0), lhs_x);
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MOVQ_xmm(R(COND0), SRC1);
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MOV(64, R(COND1), R(COND0));
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} else {
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bool invert_op_y = (op_y == Op::GreaterThan || op_y == Op::GreaterEqual);
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Gen::X64Reg lhs_y = invert_op_y ? SRC2 : SRC1;
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Gen::X64Reg rhs_y = invert_op_y ? SRC1 : SRC2;
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// Compare X-component
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MOVAPS(SCRATCH, R(SRC1));
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CMPSS(SCRATCH, R(SRC2), cmp[instr.common.compare_op.x]);
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MOVAPS(SCRATCH, R(lhs_x));
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CMPSS(SCRATCH, R(rhs_x), cmp[op_x]);
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// Compare Y-component
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CMPPS(SRC1, R(SRC2), cmp[instr.common.compare_op.y]);
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CMPPS(lhs_y, R(rhs_y), cmp[op_y]);
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MOVQ_xmm(R(COND0), SCRATCH);
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MOVQ_xmm(R(COND1), SRC1);
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MOVQ_xmm(R(COND1), lhs_y);
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}
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SHR(32, R(COND0), Imm8(31));
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@ -616,12 +639,8 @@ void JitCompiler::Compile_MAD(Instruction instr) {
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Compile_SwizzleSrc(instr, 3, instr.mad.src3, SRC3);
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}
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if (Common::GetCPUCaps().fma) {
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VFMADD213PS(SRC1, SRC2, R(SRC3));
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} else {
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MULPS(SRC1, R(SRC2));
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Compile_SanitizedMul(SRC1, SRC2, SCRATCH);
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ADDPS(SRC1, R(SRC3));
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}
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Compile_DestEnable(instr, SRC1);
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}
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@ -68,6 +68,12 @@ private:
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void Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRegister src_reg, Gen::X64Reg dest);
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void Compile_DestEnable(Instruction instr, Gen::X64Reg dest);
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/**
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* Compiles a `MUL src1, src2` operation, properly handling the PICA semantics when multiplying
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* zero by inf. Clobbers `src2` and `scratch`.
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*/
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void Compile_SanitizedMul(Gen::X64Reg src1, Gen::X64Reg src2, Gen::X64Reg scratch);
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void Compile_EvaluateCondition(Instruction instr);
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void Compile_UniformCondition(Instruction instr);
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