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Update register read loops to go with last commit
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8a0d848646
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@ -57,6 +57,7 @@ const u32 R0_REGISTER = 0;
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const u32 R15_REGISTER = 15;
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const u32 CSPR_REGISTER = 25;
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const u32 FPSCR_REGISTER = 58;
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const u32 MAX_REGISTERS = 90;
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namespace GDBStub {
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@ -487,7 +488,7 @@ static void ReadRegisters() {
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memset(buffer, 0, sizeof(buffer));
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u8* bufptr = buffer;
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for (int i = 0; i <= FPSCR_REGISTER; i++) {
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for (int i = 0; i <= MAX_REGISTERS; i++) {
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if (i <= R15_REGISTER) {
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IntToHex(bufptr + i * 8, Core::g_app_core->GetReg(i));
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} else if (i == CSPR_REGISTER) {
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@ -496,11 +497,11 @@ static void ReadRegisters() {
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IntToHex(bufptr + i * 8, 0);
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IntToHex(bufptr + (i + 1) * 8, 0);
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i++; // These registers seem to be all 64bit instead of 32bit, so skip two instead of one
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} else if (i > CSPR_REGISTER && i < FPSCR_REGISTER) {
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} else if (i > CSPR_REGISTER && i < MAX_REGISTERS) {
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IntToHex(bufptr + i * 8, Core::g_app_core->GetVFPReg(i - CSPR_REGISTER - 1));
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IntToHex(bufptr + (i + 1) * 8, 0);
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i++;
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} else if (i == FPSCR_REGISTER) {
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} else if (i == MAX_REGISTERS) {
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IntToHex(bufptr + i * 8, Core::g_app_core->GetVFPSystemReg(VFP_FPSCR));
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}
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}
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@ -541,16 +542,16 @@ static void WriteRegisters() {
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if (command_buffer[0] != 'G')
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return SendReply("E01");
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for (int i = 0; i <= FPSCR_REGISTER; i++) {
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for (int i = 0; i <= MAX_REGISTERS; i++) {
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if (i <= R15_REGISTER) {
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Core::g_app_core->SetReg(i, HexToInt(buffer_ptr + i * 8));
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} else if (i == CSPR_REGISTER) {
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Core::g_app_core->SetCPSR(HexToInt(buffer_ptr + i * 8));
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} else if (i < CSPR_REGISTER) {
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i++; // These registers seem to be all 64bit instead of 32bit, so skip two instead of one
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} else if (i > CSPR_REGISTER && i < FPSCR_REGISTER) {
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} else if (i > CSPR_REGISTER && i < MAX_REGISTERS) {
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Core::g_app_core->SetVFPReg(i - CSPR_REGISTER - 1, HexToInt(buffer_ptr + i * 8));
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} else if (i == FPSCR_REGISTER) {
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} else if (i == MAX_REGISTERS) {
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Core::g_app_core->SetVFPSystemReg(VFP_FPSCR, HexToInt(buffer_ptr + i * 8));
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}
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}
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