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dyncom: Stub MCRR and MRRC
There's no other coprocessor outside the VFP (which has its own VMOV variants) in which the MPCore can send/retrieve data from. Stubbed so citra won't crash and burn on the odd chance someone actually tries to use these.
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@ -992,6 +992,14 @@ typedef struct _mcr_inst {
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unsigned int inst;
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} mcr_inst;
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typedef struct mcrr_inst {
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unsigned int opcode_1;
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unsigned int cp_num;
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unsigned int crm;
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unsigned int rt;
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unsigned int rt2;
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} mcrr_inst;
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typedef struct _mrs_inst {
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unsigned int R;
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unsigned int Rd;
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@ -1261,11 +1269,6 @@ static get_addr_fp_t get_calc_addr_op(unsigned int inst) {
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#define CHECK_RM (inst_cream->Rm == 15)
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#define CHECK_RS (inst_cream->Rs == 15)
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#define UNIMPLEMENTED_INSTRUCTION(mnemonic) \
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LOG_ERROR(Core_ARM11, "unimplemented instruction: %s", mnemonic); \
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CITRA_IGNORE_EXIT(-1); \
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return nullptr;
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static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(adc_inst));
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@ -1871,7 +1874,26 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index)
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inst_cream->inst = inst;
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("MCRR"); }
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static ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mcrr_inst));
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mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->crm = BITS(inst, 0, 3);
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inst_cream->opcode_1 = BITS(inst, 4, 7);
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inst_cream->cp_num = BITS(inst, 8, 11);
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inst_cream->rt = BITS(inst, 12, 15);
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inst_cream->rt2 = BITS(inst, 16, 19);
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mla_inst));
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@ -1930,7 +1952,12 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index)
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inst_cream->inst = inst;
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("MRRC"); }
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static ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(mcrr)(inst, index);
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrs_inst));
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@ -4754,7 +4781,24 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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MCRR_INST:
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{
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// Stubbed, as the MPCore doesn't have any registers that are accessible
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// through this instruction.
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
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LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
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inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(mcrr_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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MLA_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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@ -4830,7 +4874,24 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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MRRC_INST:
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{
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// Stubbed, as the MPCore doesn't have any registers that are accessible
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// through this instruction.
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
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LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
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inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(mcrr_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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MRS_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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