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dyncom: Implement SETEND
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b56829df02
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@ -1075,6 +1075,10 @@ typedef struct _swp_inst {
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unsigned int Rm;
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} swp_inst;
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typedef struct setend_inst {
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unsigned int set_bigend;
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} setend_inst;
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typedef struct _b_2_thumb {
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unsigned int imm;
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}b_2_thumb;
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@ -2283,7 +2287,20 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index)
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SETEND"); }
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static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(setend_inst));
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setend_inst* const inst_cream = (setend_inst*)inst_base->component;
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inst_base->cond = AL;
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->set_bigend = BIT(inst, 9);
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index)
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{
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@ -5521,6 +5538,23 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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SETEND_INST:
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{
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// SETEND is unconditional
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setend_inst* const inst_cream = (setend_inst*)inst_base->component;
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const bool big_endian = (inst_cream->set_bigend == 1);
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if (big_endian)
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cpu->Cpsr |= (1 << 9);
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else
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cpu->Cpsr &= ~(1 << 9);
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LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE");
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(setend_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SHADD8_INST:
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SHADD16_INST:
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