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Clean up icc + ia64 situation.
Some googling turned up multiple sources saying that older versions of icc
do not accept gcc-compatible asm blocks on IA64, though asm does work on
x86[_64]. This is apparently fixed as of icc version 12.0 or so, but that
doesn't help us much; if we have to carry the extra implementation anyway,
we may as well just use it for icc rather than add a compiler version test.
Hence, revert commit 2c713d6ea2
(though I
separated the icc code from the gcc code completely, producing what seems
cleaner code). Document the state of affairs more explicitly, both in
s_lock.h and postgres.c, and make some cosmetic adjustments around the
IA64 code in s_lock.h.
This commit is contained in:
parent
049a7799df
commit
123c9d2fc1
@ -2998,6 +2998,10 @@ ProcessInterrupts(void)
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* IA64-specific code to fetch the AR.BSP register for stack depth checks.
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* IA64-specific code to fetch the AR.BSP register for stack depth checks.
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*
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*
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* We currently support gcc, icc, and HP-UX's native compiler here.
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* We currently support gcc, icc, and HP-UX's native compiler here.
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*
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* Note: while icc accepts gcc asm blocks on x86[_64], this is not true on
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* ia64 (at least not in icc versions before 12.x). So we have to carry a
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* separate implementation for it.
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*/
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*/
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#if defined(__ia64__) || defined(__ia64)
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#if defined(__ia64__) || defined(__ia64)
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@ -3005,8 +3009,12 @@ ProcessInterrupts(void)
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/* Assume it's HP-UX native compiler */
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/* Assume it's HP-UX native compiler */
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#include <ia64/sys/inline.h>
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#include <ia64/sys/inline.h>
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#define ia64_get_bsp() ((char *) (_Asm_mov_from_ar(_AREG_BSP, _NO_FENCE)))
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#define ia64_get_bsp() ((char *) (_Asm_mov_from_ar(_AREG_BSP, _NO_FENCE)))
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#elif defined(__INTEL_COMPILER)
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/* icc */
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#include <asm/ia64regs.h>
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#define ia64_get_bsp() ((char *) __getReg(_IA64_REG_AR_BSP))
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#else
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#else
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/* Use inline assembly; works with gcc and icc */
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/* gcc */
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static __inline__ char *
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static __inline__ char *
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ia64_get_bsp(void)
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ia64_get_bsp(void)
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{
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{
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@ -266,6 +266,10 @@ spin_delay(void)
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* any explicit statement on that in the gcc manual. In Intel's compiler,
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* any explicit statement on that in the gcc manual. In Intel's compiler,
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* the -m[no-]serialize-volatile option controls that, and testing shows that
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* the -m[no-]serialize-volatile option controls that, and testing shows that
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* it is enabled by default.
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* it is enabled by default.
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*
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* While icc accepts gcc asm blocks on x86[_64], this is not true on ia64
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* (at least not in icc versions before 12.x). So we have to carry a separate
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* compiler-intrinsic-based implementation for it.
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*/
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*/
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#define HAS_TEST_AND_SET
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#define HAS_TEST_AND_SET
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@ -303,6 +307,10 @@ tas(volatile slock_t *lock)
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return ret;
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return ret;
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}
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}
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/* icc can't use the regular gcc S_UNLOCK() macro either in this case */
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#define S_UNLOCK(lock) \
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do { __memory_barrier(); *(lock) = 0; } while (0)
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#endif /* __INTEL_COMPILER */
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#endif /* __INTEL_COMPILER */
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#endif /* __ia64__ || __ia64 */
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#endif /* __ia64__ || __ia64 */
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@ -671,22 +679,19 @@ typedef unsigned char slock_t;
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#endif
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#endif
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/*
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/*
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* Note that this implementation is unsafe for any platform that can speculate
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* Default implementation of S_UNLOCK() for gcc/icc.
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*
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* Note that this implementation is unsafe for any platform that can reorder
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* a memory access (either load or store) after a following store. That
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* a memory access (either load or store) after a following store. That
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* happens not to be possible x86 and most legacy architectures (some are
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* happens not to be possible on x86 and most legacy architectures (some are
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* single-processor!), but many modern systems have weaker memory ordering.
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* single-processor!), but many modern systems have weaker memory ordering.
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* Those that do must define their own version S_UNLOCK() rather than relying
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* Those that do must define their own version of S_UNLOCK() rather than
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* on this one.
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* relying on this one.
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*/
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*/
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#if !defined(S_UNLOCK)
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#if !defined(S_UNLOCK)
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#if defined(__INTEL_COMPILER)
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#define S_UNLOCK(lock) \
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do { __memory_barrier(); *(lock) = 0; } while (0)
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#else
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#define S_UNLOCK(lock) \
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#define S_UNLOCK(lock) \
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do { __asm__ __volatile__("" : : : "memory"); *(lock) = 0; } while (0)
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do { __asm__ __volatile__("" : : : "memory"); *(lock) = 0; } while (0)
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#endif
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#endif
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#endif
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#endif /* defined(__GNUC__) || defined(__INTEL_COMPILER) */
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#endif /* defined(__GNUC__) || defined(__INTEL_COMPILER) */
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@ -793,7 +798,7 @@ tas(volatile slock_t *lock)
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#if defined(__hpux) && defined(__ia64) && !defined(__GNUC__)
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#if defined(__hpux) && defined(__ia64) && !defined(__GNUC__)
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/*
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/*
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* HP-UX on Itanium, non-gcc compiler
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* HP-UX on Itanium, non-gcc/icc compiler
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*
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*
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* We assume that the compiler enforces strict ordering of loads/stores on
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* We assume that the compiler enforces strict ordering of loads/stores on
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* volatile data (see comments on the gcc-version earlier in this file).
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* volatile data (see comments on the gcc-version earlier in this file).
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@ -816,7 +821,7 @@ typedef unsigned int slock_t;
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#define S_UNLOCK(lock) \
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#define S_UNLOCK(lock) \
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do { _Asm_mf(); (*(lock)) = 0; } while (0)
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do { _Asm_mf(); (*(lock)) = 0; } while (0)
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#endif /* HPUX on IA64, non gcc */
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#endif /* HPUX on IA64, non gcc/icc */
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#if defined(_AIX) /* AIX */
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#if defined(_AIX) /* AIX */
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/*
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/*
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@ -935,7 +940,7 @@ extern int tas_sema(volatile slock_t *lock);
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#if !defined(S_UNLOCK)
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#if !defined(S_UNLOCK)
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/*
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/*
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* Our default implementation of S_UNLOCK is essentially *(lock) = 0. This
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* Our default implementation of S_UNLOCK is essentially *(lock) = 0. This
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* is unsafe if the platform can speculate a memory access (either load or
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* is unsafe if the platform can reorder a memory access (either load or
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* store) after a following store; platforms where this is possible must
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* store) after a following store; platforms where this is possible must
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* define their own S_UNLOCK. But CPU reordering is not the only concern:
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* define their own S_UNLOCK. But CPU reordering is not the only concern:
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* if we simply defined S_UNLOCK() as an inline macro, the compiler might
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* if we simply defined S_UNLOCK() as an inline macro, the compiler might
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