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Replace xlc __fetch_and_add() with inline asm.
PostgreSQL has been unusable when built with xlc 13 and newer, which are incompatible with our use of __fetch_and_add(). Back-patch to 9.5, which introduced pg_atomic_fetch_add_u32(). Reviewed by Tom Lane. Discussion: https://postgr.es/m/20190831071157.GA3251746@rfd.leadboat.com
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@ -73,11 +73,27 @@ pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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static inline uint32
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pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_)
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{
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uint32 _t;
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uint32 res;
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/*
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* __fetch_and_add() emits a leading "sync" and trailing "isync", thereby
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* providing sequential consistency. This is undocumented.
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* xlc has a no-longer-documented __fetch_and_add() intrinsic. In xlc
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* 12.01.0000.0000, it emits a leading "sync" and trailing "isync". In
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* xlc 13.01.0003.0004, it emits neither. Hence, using the intrinsic
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* would add redundant syncs on xlc 12.
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*/
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return __fetch_and_add((volatile int *)&ptr->value, add_);
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__asm__ __volatile__(
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" sync \n"
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" lwarx %1,0,%4 \n"
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" add %0,%1,%3 \n"
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" stwcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to lwarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "r"(add_), "r"(&ptr->value)
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: "memory", "cc");
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return res;
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}
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#ifdef PG_HAVE_ATOMIC_U64_SUPPORT
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@ -103,7 +119,22 @@ pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
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static inline uint64
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pg_atomic_fetch_add_u64_impl(volatile pg_atomic_uint64 *ptr, int64 add_)
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{
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return __fetch_and_addlp((volatile long *)&ptr->value, add_);
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uint64 _t;
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uint64 res;
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/* Like u32, but s/lwarx/ldarx/; s/stwcx/stdcx/ */
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__asm__ __volatile__(
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" sync \n"
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" ldarx %1,0,%4 \n"
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" add %0,%1,%3 \n"
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" stdcx. %0,0,%4 \n"
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" bne $-12 \n" /* branch to ldarx */
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" isync \n"
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: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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: "r"(add_), "r"(&ptr->value)
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: "memory", "cc");
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return res;
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}
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#endif /* PG_HAVE_ATOMIC_U64_SUPPORT */
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