From a82a5eee314df52f3183cedc0ecbcac7369243b1 Mon Sep 17 00:00:00 2001 From: Tom Lane Date: Wed, 6 Apr 2022 18:57:57 -0400 Subject: [PATCH] Use ISB as a spin-delay instruction on ARM64. This seems beneficial on high-core-count machines, and not harmful on lesser hardware. However, older ARM32 gear doesn't have this instruction, so restrict the patch to ARM64. Geoffrey Blake Discussion: https://postgr.es/m/78338F29-9D7F-4DC8-BD71-E9674CE71425@amazon.com --- src/include/storage/s_lock.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h index 8a5a905e38..af1145d98f 100644 --- a/src/include/storage/s_lock.h +++ b/src/include/storage/s_lock.h @@ -337,6 +337,23 @@ tas(volatile slock_t *lock) #define S_UNLOCK(lock) __sync_lock_release(lock) +/* + * Using an ISB instruction to delay in spinlock loops appears beneficial on + * high-core-count ARM64 processors. It seems mostly a wash for smaller gear, + * and ISB doesn't exist at all on pre-v7 ARM chips. + */ +#if defined(__aarch64__) || defined(__aarch64) + +#define SPIN_DELAY() spin_delay() + +static __inline__ void +spin_delay(void) +{ + __asm__ __volatile__( + " isb; \n"); +} + +#endif /* __aarch64__ || __aarch64 */ #endif /* HAVE_GCC__SYNC_INT32_TAS */ #endif /* __arm__ || __arm || __aarch64__ || __aarch64 */