107 lines
2.8 KiB
C
107 lines
2.8 KiB
C
/*-------------------------------------------------------------------------
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*
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* generic-acc.h
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* Atomic operations support when using HPs acc on HPUX
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*
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* Portions Copyright (c) 1996-2022, PostgreSQL Global Development Group
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* Portions Copyright (c) 1994, Regents of the University of California
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*
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* NOTES:
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*
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* Documentation:
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* * inline assembly for Itanium-based HP-UX:
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* http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/inline_assem_ERS.pdf
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* * Implementing Spinlocks on the Intel (R) Itanium (R) Architecture and PA-RISC
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* http://h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf
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*
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* Itanium only supports a small set of numbers (6, -8, -4, -1, 1, 4, 8, 16)
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* for atomic add/sub, so we just implement everything but compare_exchange
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* via the compare_exchange fallbacks in atomics/generic.h.
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*
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* src/include/port/atomics/generic-acc.h
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*
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* -------------------------------------------------------------------------
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*/
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#include <machine/sys/inline.h>
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#define pg_compiler_barrier_impl() _Asm_sched_fence()
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#if defined(HAVE_ATOMICS)
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/* IA64 always has 32/64 bit atomics */
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#define PG_HAVE_ATOMIC_U32_SUPPORT
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typedef struct pg_atomic_uint32
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{
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volatile uint32 value;
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} pg_atomic_uint32;
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#define PG_HAVE_ATOMIC_U64_SUPPORT
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typedef struct pg_atomic_uint64
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{
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/*
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* Alignment is guaranteed to be 64bit. Search for "Well-behaved
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* application restrictions" => "Data alignment and data sharing" on HP's
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* website. Unfortunately the URL doesn't seem to stable enough to
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* include.
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*/
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volatile uint64 value;
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} pg_atomic_uint64;
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#define MINOR_FENCE (_Asm_fence) (_UP_CALL_FENCE | _UP_SYS_FENCE | \
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_DOWN_CALL_FENCE | _DOWN_SYS_FENCE )
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#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U32
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static inline bool
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pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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uint32 *expected, uint32 newval)
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{
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bool ret;
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uint32 current;
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_Asm_mov_to_ar(_AREG_CCV, *expected, MINOR_FENCE);
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/*
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* We want a barrier, not just release/acquire semantics.
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*/
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_Asm_mf();
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/*
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* Notes:
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* _DOWN_MEM_FENCE | _UP_MEM_FENCE prevents reordering by the compiler
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*/
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current = _Asm_cmpxchg(_SZ_W, /* word */
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_SEM_REL,
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&ptr->value,
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newval, _LDHINT_NONE,
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_DOWN_MEM_FENCE | _UP_MEM_FENCE);
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ret = current == *expected;
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*expected = current;
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return ret;
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}
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#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U64
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static inline bool
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pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
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uint64 *expected, uint64 newval)
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{
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bool ret;
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uint64 current;
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_Asm_mov_to_ar(_AREG_CCV, *expected, MINOR_FENCE);
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_Asm_mf();
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current = _Asm_cmpxchg(_SZ_D, /* doubleword */
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_SEM_REL,
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&ptr->value,
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newval, _LDHINT_NONE,
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_DOWN_MEM_FENCE | _UP_MEM_FENCE);
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ret = current == *expected;
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*expected = current;
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return ret;
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}
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#undef MINOR_FENCE
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#endif /* defined(HAVE_ATOMICS) */
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