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a4777f3556
This used to mean "Visual C++ except in those parts where Borland C++ was supported where it meant one of those". Now that we don't support Borland C++ anymore, simplify by using _MSC_VER which is the normal way to detect Visual C++.
1002 lines
28 KiB
C
1002 lines
28 KiB
C
/*-------------------------------------------------------------------------
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*
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* s_lock.h
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* Hardware-dependent implementation of spinlocks.
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*
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* NOTE: none of the macros in this file are intended to be called directly.
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* Call them through the hardware-independent macros in spin.h.
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*
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* The following hardware-dependent macros must be provided for each
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* supported platform:
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*
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* void S_INIT_LOCK(slock_t *lock)
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* Initialize a spinlock (to the unlocked state).
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*
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* int S_LOCK(slock_t *lock)
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* Acquire a spinlock, waiting if necessary.
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* Time out and abort() if unable to acquire the lock in a
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* "reasonable" amount of time --- typically ~ 1 minute.
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* Should return number of "delays"; see s_lock.c
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*
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* void S_UNLOCK(slock_t *lock)
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* Unlock a previously acquired lock.
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*
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* bool S_LOCK_FREE(slock_t *lock)
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* Tests if the lock is free. Returns TRUE if free, FALSE if locked.
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* This does *not* change the state of the lock.
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*
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* void SPIN_DELAY(void)
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* Delay operation to occur inside spinlock wait loop.
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*
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* Note to implementors: there are default implementations for all these
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* macros at the bottom of the file. Check if your platform can use
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* these or needs to override them.
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*
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* Usually, S_LOCK() is implemented in terms of even lower-level macros
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* TAS() and TAS_SPIN():
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*
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* int TAS(slock_t *lock)
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* Atomic test-and-set instruction. Attempt to acquire the lock,
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* but do *not* wait. Returns 0 if successful, nonzero if unable
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* to acquire the lock.
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*
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* int TAS_SPIN(slock_t *lock)
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* Like TAS(), but this version is used when waiting for a lock
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* previously found to be contended. By default, this is the
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* same as TAS(), but on some architectures it's better to poll a
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* contended lock using an unlocked instruction and retry the
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* atomic test-and-set only when it appears free.
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*
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* TAS() and TAS_SPIN() are NOT part of the API, and should never be called
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* directly.
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*
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* CAUTION: on some platforms TAS() and/or TAS_SPIN() may sometimes report
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* failure to acquire a lock even when the lock is not locked. For example,
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* on Alpha TAS() will "fail" if interrupted. Therefore a retry loop must
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* always be used, even if you are certain the lock is free.
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*
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* It is the responsibility of these macros to make sure that the compiler
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* does not re-order accesses to shared memory to precede the actual lock
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* acquisition, or follow the lock release. Prior to PostgreSQL 9.5, this
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* was the caller's responsibility, which meant that callers had to use
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* volatile-qualified pointers to refer to both the spinlock itself and the
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* shared data being accessed within the spinlocked critical section. This
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* was notationally awkward, easy to forget (and thus error-prone), and
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* prevented some useful compiler optimizations. For these reasons, we
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* now require that the macros themselves prevent compiler re-ordering,
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* so that the caller doesn't need to take special precautions.
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*
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* On platforms with weak memory ordering, the TAS(), TAS_SPIN(), and
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* S_UNLOCK() macros must further include hardware-level memory fence
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* instructions to prevent similar re-ordering at the hardware level.
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* TAS() and TAS_SPIN() must guarantee that loads and stores issued after
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* the macro are not executed until the lock has been obtained. Conversely,
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* S_UNLOCK() must guarantee that loads and stores issued before the macro
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* have been executed before the lock is released.
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*
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* On most supported platforms, TAS() uses a tas() function written
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* in assembly language to execute a hardware atomic-test-and-set
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* instruction. Equivalent OS-supplied mutex routines could be used too.
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*
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* If no system-specific TAS() is available (ie, HAVE_SPINLOCKS is not
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* defined), then we fall back on an emulation that uses SysV semaphores
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* (see spin.c). This emulation will be MUCH MUCH slower than a proper TAS()
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* implementation, because of the cost of a kernel call per lock or unlock.
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* An old report is that Postgres spends around 40% of its time in semop(2)
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* when using the SysV semaphore code.
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*
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*
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* Portions Copyright (c) 1996-2017, PostgreSQL Global Development Group
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* Portions Copyright (c) 1994, Regents of the University of California
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*
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* src/include/storage/s_lock.h
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*
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*-------------------------------------------------------------------------
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*/
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#ifndef S_LOCK_H
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#define S_LOCK_H
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#ifdef FRONTEND
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#error "s_lock.h may not be included from frontend code"
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#endif
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#ifdef HAVE_SPINLOCKS /* skip spinlocks if requested */
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#if defined(__GNUC__) || defined(__INTEL_COMPILER)
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/*************************************************************************
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* All the gcc inlines
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* Gcc consistently defines the CPU as __cpu__.
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* Other compilers use __cpu or __cpu__ so we test for both in those cases.
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*/
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/*----------
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* Standard gcc asm format (assuming "volatile slock_t *lock"):
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__asm__ __volatile__(
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" instruction \n"
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" instruction \n"
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" instruction \n"
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: "=r"(_res), "+m"(*lock) // return register, in/out lock value
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: "r"(lock) // lock pointer, in input register
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: "memory", "cc"); // show clobbered registers here
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* The output-operands list (after first colon) should always include
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* "+m"(*lock), whether or not the asm code actually refers to this
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* operand directly. This ensures that gcc believes the value in the
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* lock variable is used and set by the asm code. Also, the clobbers
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* list (after third colon) should always include "memory"; this prevents
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* gcc from thinking it can cache the values of shared-memory fields
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* across the asm code. Add "cc" if your asm code changes the condition
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* code register, and also list any temp registers the code uses.
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*----------
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*/
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#ifdef __i386__ /* 32-bit i386 */
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#define HAS_TEST_AND_SET
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typedef unsigned char slock_t;
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#define TAS(lock) tas(lock)
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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register slock_t _res = 1;
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/*
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* Use a non-locking test before asserting the bus lock. Note that the
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* extra test appears to be a small loss on some x86 platforms and a small
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* win on others; it's by no means clear that we should keep it.
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*
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* When this was last tested, we didn't have separate TAS() and TAS_SPIN()
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* macros. Nowadays it probably would be better to do a non-locking test
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* in TAS_SPIN() but not in TAS(), like on x86_64, but no-one's done the
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* testing to verify that. Without some empirical evidence, better to
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* leave it alone.
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*/
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__asm__ __volatile__(
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" cmpb $0,%1 \n"
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" jne 1f \n"
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" lock \n"
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" xchgb %0,%1 \n"
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"1: \n"
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: "+q"(_res), "+m"(*lock)
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: /* no inputs */
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: "memory", "cc");
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return (int) _res;
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}
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#define SPIN_DELAY() spin_delay()
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static __inline__ void
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spin_delay(void)
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{
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/*
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* This sequence is equivalent to the PAUSE instruction ("rep" is
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* ignored by old IA32 processors if the following instruction is
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* not a string operation); the IA-32 Architecture Software
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* Developer's Manual, Vol. 3, Section 7.7.2 describes why using
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* PAUSE in the inner loop of a spin lock is necessary for good
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* performance:
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*
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* The PAUSE instruction improves the performance of IA-32
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* processors supporting Hyper-Threading Technology when
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* executing spin-wait loops and other routines where one
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* thread is accessing a shared lock or semaphore in a tight
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* polling loop. When executing a spin-wait loop, the
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* processor can suffer a severe performance penalty when
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* exiting the loop because it detects a possible memory order
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* violation and flushes the core processor's pipeline. The
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* PAUSE instruction provides a hint to the processor that the
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* code sequence is a spin-wait loop. The processor uses this
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* hint to avoid the memory order violation and prevent the
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* pipeline flush. In addition, the PAUSE instruction
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* de-pipelines the spin-wait loop to prevent it from
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* consuming execution resources excessively.
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*/
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__asm__ __volatile__(
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" rep; nop \n");
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}
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#endif /* __i386__ */
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#ifdef __x86_64__ /* AMD Opteron, Intel EM64T */
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#define HAS_TEST_AND_SET
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typedef unsigned char slock_t;
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#define TAS(lock) tas(lock)
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/*
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* On Intel EM64T, it's a win to use a non-locking test before the xchg proper,
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* but only when spinning.
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*
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* See also Implementing Scalable Atomic Locks for Multi-Core Intel(tm) EM64T
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* and IA32, by Michael Chynoweth and Mary R. Lee. As of this writing, it is
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* available at:
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* http://software.intel.com/en-us/articles/implementing-scalable-atomic-locks-for-multi-core-intel-em64t-and-ia32-architectures
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*/
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#define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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register slock_t _res = 1;
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__asm__ __volatile__(
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" lock \n"
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" xchgb %0,%1 \n"
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: "+q"(_res), "+m"(*lock)
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: /* no inputs */
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: "memory", "cc");
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return (int) _res;
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}
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#define SPIN_DELAY() spin_delay()
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static __inline__ void
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spin_delay(void)
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{
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/*
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* Adding a PAUSE in the spin delay loop is demonstrably a no-op on
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* Opteron, but it may be of some use on EM64T, so we keep it.
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*/
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__asm__ __volatile__(
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" rep; nop \n");
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}
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#endif /* __x86_64__ */
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#if defined(__ia64__) || defined(__ia64)
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/*
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* Intel Itanium, gcc or Intel's compiler.
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*
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* Itanium has weak memory ordering, but we rely on the compiler to enforce
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* strict ordering of accesses to volatile data. In particular, while the
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* xchg instruction implicitly acts as a memory barrier with 'acquire'
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* semantics, we do not have an explicit memory fence instruction in the
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* S_UNLOCK macro. We use a regular assignment to clear the spinlock, and
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* trust that the compiler marks the generated store instruction with the
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* ".rel" opcode.
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*
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* Testing shows that assumption to hold on gcc, although I could not find
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* any explicit statement on that in the gcc manual. In Intel's compiler,
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* the -m[no-]serialize-volatile option controls that, and testing shows that
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* it is enabled by default.
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*
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* While icc accepts gcc asm blocks on x86[_64], this is not true on ia64
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* (at least not in icc versions before 12.x). So we have to carry a separate
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* compiler-intrinsic-based implementation for it.
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*/
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#define HAS_TEST_AND_SET
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typedef unsigned int slock_t;
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#define TAS(lock) tas(lock)
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/* On IA64, it's a win to use a non-locking test before the xchg proper */
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#define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
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#ifndef __INTEL_COMPILER
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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long int ret;
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__asm__ __volatile__(
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" xchg4 %0=%1,%2 \n"
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: "=r"(ret), "+m"(*lock)
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: "r"(1)
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: "memory");
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return (int) ret;
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}
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#else /* __INTEL_COMPILER */
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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int ret;
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ret = _InterlockedExchange(lock,1); /* this is a xchg asm macro */
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return ret;
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}
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/* icc can't use the regular gcc S_UNLOCK() macro either in this case */
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#define S_UNLOCK(lock) \
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do { __memory_barrier(); *(lock) = 0; } while (0)
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#endif /* __INTEL_COMPILER */
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#endif /* __ia64__ || __ia64 */
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/*
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* On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
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*
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* We use the int-width variant of the builtin because it works on more chips
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* than other widths.
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*/
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#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64)
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#ifdef HAVE_GCC__SYNC_INT32_TAS
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#define HAS_TEST_AND_SET
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#define TAS(lock) tas(lock)
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typedef int slock_t;
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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return __sync_lock_test_and_set(lock, 1);
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}
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#define S_UNLOCK(lock) __sync_lock_release(lock)
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#endif /* HAVE_GCC__SYNC_INT32_TAS */
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#endif /* __arm__ || __arm || __aarch64__ || __aarch64 */
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/* S/390 and S/390x Linux (32- and 64-bit zSeries) */
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#if defined(__s390__) || defined(__s390x__)
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#define HAS_TEST_AND_SET
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typedef unsigned int slock_t;
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#define TAS(lock) tas(lock)
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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int _res = 0;
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__asm__ __volatile__(
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" cs %0,%3,0(%2) \n"
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: "+d"(_res), "+m"(*lock)
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: "a"(lock), "d"(1)
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: "memory", "cc");
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return _res;
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}
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#endif /* __s390__ || __s390x__ */
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#if defined(__sparc__) /* Sparc */
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/*
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* Solaris has always run sparc processors in TSO (total store) mode, but
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* linux didn't use to and the *BSDs still don't. So, be careful about
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* acquire/release semantics. The CPU will treat superfluous membars as
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* NOPs, so it's just code space.
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*/
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#define HAS_TEST_AND_SET
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typedef unsigned char slock_t;
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#define TAS(lock) tas(lock)
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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register slock_t _res;
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/*
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* See comment in /pg/backend/port/tas/solaris_sparc.s for why this
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* uses "ldstub", and that file uses "cas". gcc currently generates
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* sparcv7-targeted binaries, so "cas" use isn't possible.
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*/
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__asm__ __volatile__(
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" ldstub [%2], %0 \n"
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: "=r"(_res), "+m"(*lock)
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: "r"(lock)
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: "memory");
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#if defined(__sparcv7) || defined(__sparc_v7__)
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/*
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* No stbar or membar available, luckily no actually produced hardware
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* requires a barrier.
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*/
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#elif defined(__sparcv8) || defined(__sparc_v8__)
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/* stbar is available (and required for both PSO, RMO), membar isn't */
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__asm__ __volatile__ ("stbar \n":::"memory");
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#else
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/*
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* #LoadStore (RMO) | #LoadLoad (RMO) together are the appropriate acquire
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* barrier for sparcv8+ upwards.
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*/
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__asm__ __volatile__ ("membar #LoadStore | #LoadLoad \n":::"memory");
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#endif
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return (int) _res;
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}
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#if defined(__sparcv7) || defined(__sparc_v7__)
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/*
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* No stbar or membar available, luckily no actually produced hardware
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* requires a barrier. We fall through to the default gcc definition of
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* S_UNLOCK in this case.
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*/
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#elif defined(__sparcv8) || defined(__sparc_v8__)
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/* stbar is available (and required for both PSO, RMO), membar isn't */
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#define S_UNLOCK(lock) \
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do \
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{ \
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__asm__ __volatile__ ("stbar \n":::"memory"); \
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*((volatile slock_t *) (lock)) = 0; \
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} while (0)
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#else
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/*
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* #LoadStore (RMO) | #StoreStore (RMO, PSO) together are the appropriate
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* release barrier for sparcv8+ upwards.
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*/
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#define S_UNLOCK(lock) \
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do \
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{ \
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__asm__ __volatile__ ("membar #LoadStore | #StoreStore \n":::"memory"); \
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*((volatile slock_t *) (lock)) = 0; \
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} while (0)
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#endif
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#endif /* __sparc__ */
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/* PowerPC */
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#if defined(__ppc__) || defined(__powerpc__) || defined(__ppc64__) || defined(__powerpc64__)
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#define HAS_TEST_AND_SET
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typedef unsigned int slock_t;
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#define TAS(lock) tas(lock)
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/* On PPC, it's a win to use a non-locking test before the lwarx */
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#define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
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/*
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* NOTE: per the Enhanced PowerPC Architecture manual, v1.0 dated 7-May-2002,
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* an isync is a sufficient synchronization barrier after a lwarx/stwcx loop.
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* On newer machines, we can use lwsync instead for better performance.
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*
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* Ordinarily, we'd code the branches here using GNU-style local symbols, that
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* is "1f" referencing "1:" and so on. But some people run gcc on AIX with
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* IBM's assembler as backend, and IBM's assembler doesn't do local symbols.
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* So hand-code the branch offsets; fortunately, all PPC instructions are
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* exactly 4 bytes each, so it's not too hard to count.
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*/
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static __inline__ int
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tas(volatile slock_t *lock)
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{
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slock_t _t;
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int _res;
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__asm__ __volatile__(
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#ifdef USE_PPC_LWARX_MUTEX_HINT
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" lwarx %0,0,%3,1 \n"
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#else
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" lwarx %0,0,%3 \n"
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#endif
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" cmpwi %0,0 \n"
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" bne $+16 \n" /* branch to li %1,1 */
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" addi %0,%0,1 \n"
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" stwcx. %0,0,%3 \n"
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" beq $+12 \n" /* branch to lwsync/isync */
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" li %1,1 \n"
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" b $+12 \n" /* branch to end of asm sequence */
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#ifdef USE_PPC_LWSYNC
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" lwsync \n"
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#else
|
|
" isync \n"
|
|
#endif
|
|
" li %1,0 \n"
|
|
|
|
: "=&r"(_t), "=r"(_res), "+m"(*lock)
|
|
: "r"(lock)
|
|
: "memory", "cc");
|
|
return _res;
|
|
}
|
|
|
|
/*
|
|
* PowerPC S_UNLOCK is almost standard but requires a "sync" instruction.
|
|
* On newer machines, we can use lwsync instead for better performance.
|
|
*/
|
|
#ifdef USE_PPC_LWSYNC
|
|
#define S_UNLOCK(lock) \
|
|
do \
|
|
{ \
|
|
__asm__ __volatile__ (" lwsync \n" ::: "memory"); \
|
|
*((volatile slock_t *) (lock)) = 0; \
|
|
} while (0)
|
|
#else
|
|
#define S_UNLOCK(lock) \
|
|
do \
|
|
{ \
|
|
__asm__ __volatile__ (" sync \n" ::: "memory"); \
|
|
*((volatile slock_t *) (lock)) = 0; \
|
|
} while (0)
|
|
#endif /* USE_PPC_LWSYNC */
|
|
|
|
#endif /* powerpc */
|
|
|
|
|
|
/* Linux Motorola 68k */
|
|
#if (defined(__mc68000__) || defined(__m68k__)) && defined(__linux__)
|
|
#define HAS_TEST_AND_SET
|
|
|
|
typedef unsigned char slock_t;
|
|
|
|
#define TAS(lock) tas(lock)
|
|
|
|
static __inline__ int
|
|
tas(volatile slock_t *lock)
|
|
{
|
|
register int rv;
|
|
|
|
__asm__ __volatile__(
|
|
" clrl %0 \n"
|
|
" tas %1 \n"
|
|
" sne %0 \n"
|
|
: "=d"(rv), "+m"(*lock)
|
|
: /* no inputs */
|
|
: "memory", "cc");
|
|
return rv;
|
|
}
|
|
|
|
#endif /* (__mc68000__ || __m68k__) && __linux__ */
|
|
|
|
|
|
/*
|
|
* VAXen -- even multiprocessor ones
|
|
* (thanks to Tom Ivar Helbekkmo)
|
|
*/
|
|
#if defined(__vax__)
|
|
#define HAS_TEST_AND_SET
|
|
|
|
typedef unsigned char slock_t;
|
|
|
|
#define TAS(lock) tas(lock)
|
|
|
|
static __inline__ int
|
|
tas(volatile slock_t *lock)
|
|
{
|
|
register int _res;
|
|
|
|
__asm__ __volatile__(
|
|
" movl $1, %0 \n"
|
|
" bbssi $0, (%2), 1f \n"
|
|
" clrl %0 \n"
|
|
"1: \n"
|
|
: "=&r"(_res), "+m"(*lock)
|
|
: "r"(lock)
|
|
: "memory");
|
|
return _res;
|
|
}
|
|
|
|
#endif /* __vax__ */
|
|
|
|
|
|
#if defined(__mips__) && !defined(__sgi) /* non-SGI MIPS */
|
|
/* Note: on SGI we use the OS' mutex ABI, see below */
|
|
/* Note: R10000 processors require a separate SYNC */
|
|
#define HAS_TEST_AND_SET
|
|
|
|
typedef unsigned int slock_t;
|
|
|
|
#define TAS(lock) tas(lock)
|
|
|
|
static __inline__ int
|
|
tas(volatile slock_t *lock)
|
|
{
|
|
register volatile slock_t *_l = lock;
|
|
register int _res;
|
|
register int _tmp;
|
|
|
|
__asm__ __volatile__(
|
|
" .set push \n"
|
|
" .set mips2 \n"
|
|
" .set noreorder \n"
|
|
" .set nomacro \n"
|
|
" ll %0, %2 \n"
|
|
" or %1, %0, 1 \n"
|
|
" sc %1, %2 \n"
|
|
" xori %1, 1 \n"
|
|
" or %0, %0, %1 \n"
|
|
" sync \n"
|
|
" .set pop "
|
|
: "=&r" (_res), "=&r" (_tmp), "+R" (*_l)
|
|
: /* no inputs */
|
|
: "memory");
|
|
return _res;
|
|
}
|
|
|
|
/* MIPS S_UNLOCK is almost standard but requires a "sync" instruction */
|
|
#define S_UNLOCK(lock) \
|
|
do \
|
|
{ \
|
|
__asm__ __volatile__( \
|
|
" .set push \n" \
|
|
" .set mips2 \n" \
|
|
" .set noreorder \n" \
|
|
" .set nomacro \n" \
|
|
" sync \n" \
|
|
" .set pop " \
|
|
: /* no outputs */ \
|
|
: /* no inputs */ \
|
|
: "memory"); \
|
|
*((volatile slock_t *) (lock)) = 0; \
|
|
} while (0)
|
|
|
|
#endif /* __mips__ && !__sgi */
|
|
|
|
|
|
#if defined(__m32r__) && defined(HAVE_SYS_TAS_H) /* Renesas' M32R */
|
|
#define HAS_TEST_AND_SET
|
|
|
|
#include <sys/tas.h>
|
|
|
|
typedef int slock_t;
|
|
|
|
#define TAS(lock) tas(lock)
|
|
|
|
#endif /* __m32r__ */
|
|
|
|
|
|
#if defined(__sh__) /* Renesas' SuperH */
|
|
#define HAS_TEST_AND_SET
|
|
|
|
typedef unsigned char slock_t;
|
|
|
|
#define TAS(lock) tas(lock)
|
|
|
|
static __inline__ int
|
|
tas(volatile slock_t *lock)
|
|
{
|
|
register int _res;
|
|
|
|
/*
|
|
* This asm is coded as if %0 could be any register, but actually SuperH
|
|
* restricts the target of xor-immediate to be R0. That's handled by
|
|
* the "z" constraint on _res.
|
|
*/
|
|
__asm__ __volatile__(
|
|
" tas.b @%2 \n"
|
|
" movt %0 \n"
|
|
" xor #1,%0 \n"
|
|
: "=z"(_res), "+m"(*lock)
|
|
: "r"(lock)
|
|
: "memory", "t");
|
|
return _res;
|
|
}
|
|
|
|
#endif /* __sh__ */
|
|
|
|
|
|
/* These live in s_lock.c, but only for gcc */
|
|
|
|
|
|
#if defined(__m68k__) && !defined(__linux__) /* non-Linux Motorola 68k */
|
|
#define HAS_TEST_AND_SET
|
|
|
|
typedef unsigned char slock_t;
|
|
#endif
|
|
|
|
/*
|
|
* Default implementation of S_UNLOCK() for gcc/icc.
|
|
*
|
|
* Note that this implementation is unsafe for any platform that can reorder
|
|
* a memory access (either load or store) after a following store. That
|
|
* happens not to be possible on x86 and most legacy architectures (some are
|
|
* single-processor!), but many modern systems have weaker memory ordering.
|
|
* Those that do must define their own version of S_UNLOCK() rather than
|
|
* relying on this one.
|
|
*/
|
|
#if !defined(S_UNLOCK)
|
|
#define S_UNLOCK(lock) \
|
|
do { __asm__ __volatile__("" : : : "memory"); *(lock) = 0; } while (0)
|
|
#endif
|
|
|
|
#endif /* defined(__GNUC__) || defined(__INTEL_COMPILER) */
|
|
|
|
|
|
|
|
/*
|
|
* ---------------------------------------------------------------------
|
|
* Platforms that use non-gcc inline assembly:
|
|
* ---------------------------------------------------------------------
|
|
*/
|
|
|
|
#if !defined(HAS_TEST_AND_SET) /* We didn't trigger above, let's try here */
|
|
|
|
|
|
#if defined(__hppa) || defined(__hppa__) /* HP PA-RISC, GCC and HP compilers */
|
|
/*
|
|
* HP's PA-RISC
|
|
*
|
|
* See src/backend/port/hpux/tas.c.template for details about LDCWX. Because
|
|
* LDCWX requires a 16-byte-aligned address, we declare slock_t as a 16-byte
|
|
* struct. The active word in the struct is whichever has the aligned address;
|
|
* the other three words just sit at -1.
|
|
*
|
|
* When using gcc, we can inline the required assembly code.
|
|
*/
|
|
#define HAS_TEST_AND_SET
|
|
|
|
typedef struct
|
|
{
|
|
int sema[4];
|
|
} slock_t;
|
|
|
|
#define TAS_ACTIVE_WORD(lock) ((volatile int *) (((uintptr_t) (lock) + 15) & ~15))
|
|
|
|
#if defined(__GNUC__)
|
|
|
|
static __inline__ int
|
|
tas(volatile slock_t *lock)
|
|
{
|
|
volatile int *lockword = TAS_ACTIVE_WORD(lock);
|
|
register int lockval;
|
|
|
|
__asm__ __volatile__(
|
|
" ldcwx 0(0,%2),%0 \n"
|
|
: "=r"(lockval), "+m"(*lockword)
|
|
: "r"(lockword)
|
|
: "memory");
|
|
return (lockval == 0);
|
|
}
|
|
|
|
/*
|
|
* The hppa implementation doesn't follow the rules of this files and provides
|
|
* a gcc specific implementation outside of the above defined(__GNUC__). It
|
|
* does so to avoid duplication between the HP compiler and gcc. So undefine
|
|
* the generic fallback S_UNLOCK from above.
|
|
*/
|
|
#ifdef S_UNLOCK
|
|
#undef S_UNLOCK
|
|
#endif
|
|
#define S_UNLOCK(lock) \
|
|
do { \
|
|
__asm__ __volatile__("" : : : "memory"); \
|
|
*TAS_ACTIVE_WORD(lock) = -1; \
|
|
} while (0)
|
|
|
|
#endif /* __GNUC__ */
|
|
|
|
#define S_INIT_LOCK(lock) \
|
|
do { \
|
|
volatile slock_t *lock_ = (lock); \
|
|
lock_->sema[0] = -1; \
|
|
lock_->sema[1] = -1; \
|
|
lock_->sema[2] = -1; \
|
|
lock_->sema[3] = -1; \
|
|
} while (0)
|
|
|
|
#define S_LOCK_FREE(lock) (*TAS_ACTIVE_WORD(lock) != 0)
|
|
|
|
#endif /* __hppa || __hppa__ */
|
|
|
|
|
|
#if defined(__hpux) && defined(__ia64) && !defined(__GNUC__)
|
|
/*
|
|
* HP-UX on Itanium, non-gcc/icc compiler
|
|
*
|
|
* We assume that the compiler enforces strict ordering of loads/stores on
|
|
* volatile data (see comments on the gcc-version earlier in this file).
|
|
* Note that this assumption does *not* hold if you use the
|
|
* +Ovolatile=__unordered option on the HP-UX compiler, so don't do that.
|
|
*
|
|
* See also Implementing Spinlocks on the Intel Itanium Architecture and
|
|
* PA-RISC, by Tor Ekqvist and David Graves, for more information. As of
|
|
* this writing, version 1.0 of the manual is available at:
|
|
* http://h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf
|
|
*/
|
|
#define HAS_TEST_AND_SET
|
|
|
|
typedef unsigned int slock_t;
|
|
|
|
#include <ia64/sys/inline.h>
|
|
#define TAS(lock) _Asm_xchg(_SZ_W, lock, 1, _LDHINT_NONE)
|
|
/* On IA64, it's a win to use a non-locking test before the xchg proper */
|
|
#define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
|
|
#define S_UNLOCK(lock) \
|
|
do { _Asm_mf(); (*(lock)) = 0; } while (0)
|
|
|
|
#endif /* HPUX on IA64, non gcc/icc */
|
|
|
|
#if defined(_AIX) /* AIX */
|
|
/*
|
|
* AIX (POWER)
|
|
*/
|
|
#define HAS_TEST_AND_SET
|
|
|
|
#include <sys/atomic_op.h>
|
|
|
|
typedef int slock_t;
|
|
|
|
#define TAS(lock) _check_lock((slock_t *) (lock), 0, 1)
|
|
#define S_UNLOCK(lock) _clear_lock((slock_t *) (lock), 0)
|
|
#endif /* _AIX */
|
|
|
|
|
|
/* These are in sunstudio_(sparc|x86).s */
|
|
|
|
#if defined(__SUNPRO_C) && (defined(__i386) || defined(__x86_64__) || defined(__sparc__) || defined(__sparc))
|
|
#define HAS_TEST_AND_SET
|
|
|
|
#if defined(__i386) || defined(__x86_64__) || defined(__sparcv9) || defined(__sparcv8plus)
|
|
typedef unsigned int slock_t;
|
|
#else
|
|
typedef unsigned char slock_t;
|
|
#endif
|
|
|
|
extern slock_t pg_atomic_cas(volatile slock_t *lock, slock_t with,
|
|
slock_t cmp);
|
|
|
|
#define TAS(a) (pg_atomic_cas((a), 1, 0) != 0)
|
|
#endif
|
|
|
|
|
|
#ifdef _MSC_VER
|
|
typedef LONG slock_t;
|
|
|
|
#define HAS_TEST_AND_SET
|
|
#define TAS(lock) (InterlockedCompareExchange(lock, 1, 0))
|
|
|
|
#define SPIN_DELAY() spin_delay()
|
|
|
|
/* If using Visual C++ on Win64, inline assembly is unavailable.
|
|
* Use a _mm_pause intrinsic instead of rep nop.
|
|
*/
|
|
#if defined(_WIN64)
|
|
static __forceinline void
|
|
spin_delay(void)
|
|
{
|
|
_mm_pause();
|
|
}
|
|
#else
|
|
static __forceinline void
|
|
spin_delay(void)
|
|
{
|
|
/* See comment for gcc code. Same code, MASM syntax */
|
|
__asm rep nop;
|
|
}
|
|
#endif
|
|
|
|
#include <intrin.h>
|
|
#pragma intrinsic(_ReadWriteBarrier)
|
|
|
|
#define S_UNLOCK(lock) \
|
|
do { _ReadWriteBarrier(); (*(lock)) = 0; } while (0)
|
|
|
|
#endif
|
|
|
|
|
|
#endif /* !defined(HAS_TEST_AND_SET) */
|
|
|
|
|
|
/* Blow up if we didn't have any way to do spinlocks */
|
|
#ifndef HAS_TEST_AND_SET
|
|
#error PostgreSQL does not have native spinlock support on this platform. To continue the compilation, rerun configure using --disable-spinlocks. However, performance will be poor. Please report this to pgsql-bugs@postgresql.org.
|
|
#endif
|
|
|
|
|
|
#else /* !HAVE_SPINLOCKS */
|
|
|
|
|
|
/*
|
|
* Fake spinlock implementation using semaphores --- slow and prone
|
|
* to fall foul of kernel limits on number of semaphores, so don't use this
|
|
* unless you must! The subroutines appear in spin.c.
|
|
*/
|
|
typedef int slock_t;
|
|
|
|
extern bool s_lock_free_sema(volatile slock_t *lock);
|
|
extern void s_unlock_sema(volatile slock_t *lock);
|
|
extern void s_init_lock_sema(volatile slock_t *lock, bool nested);
|
|
extern int tas_sema(volatile slock_t *lock);
|
|
|
|
#define S_LOCK_FREE(lock) s_lock_free_sema(lock)
|
|
#define S_UNLOCK(lock) s_unlock_sema(lock)
|
|
#define S_INIT_LOCK(lock) s_init_lock_sema(lock, false)
|
|
#define TAS(lock) tas_sema(lock)
|
|
|
|
|
|
#endif /* HAVE_SPINLOCKS */
|
|
|
|
|
|
/*
|
|
* Default Definitions - override these above as needed.
|
|
*/
|
|
|
|
#if !defined(S_LOCK)
|
|
#define S_LOCK(lock) \
|
|
(TAS(lock) ? s_lock((lock), __FILE__, __LINE__, PG_FUNCNAME_MACRO) : 0)
|
|
#endif /* S_LOCK */
|
|
|
|
#if !defined(S_LOCK_FREE)
|
|
#define S_LOCK_FREE(lock) (*(lock) == 0)
|
|
#endif /* S_LOCK_FREE */
|
|
|
|
#if !defined(S_UNLOCK)
|
|
/*
|
|
* Our default implementation of S_UNLOCK is essentially *(lock) = 0. This
|
|
* is unsafe if the platform can reorder a memory access (either load or
|
|
* store) after a following store; platforms where this is possible must
|
|
* define their own S_UNLOCK. But CPU reordering is not the only concern:
|
|
* if we simply defined S_UNLOCK() as an inline macro, the compiler might
|
|
* reorder instructions from inside the critical section to occur after the
|
|
* lock release. Since the compiler probably can't know what the external
|
|
* function s_unlock is doing, putting the same logic there should be adequate.
|
|
* A sufficiently-smart globally optimizing compiler could break that
|
|
* assumption, though, and the cost of a function call for every spinlock
|
|
* release may hurt performance significantly, so we use this implementation
|
|
* only for platforms where we don't know of a suitable intrinsic. For the
|
|
* most part, those are relatively obscure platform/compiler combinations to
|
|
* which the PostgreSQL project does not have access.
|
|
*/
|
|
#define USE_DEFAULT_S_UNLOCK
|
|
extern void s_unlock(volatile slock_t *lock);
|
|
#define S_UNLOCK(lock) s_unlock(lock)
|
|
#endif /* S_UNLOCK */
|
|
|
|
#if !defined(S_INIT_LOCK)
|
|
#define S_INIT_LOCK(lock) S_UNLOCK(lock)
|
|
#endif /* S_INIT_LOCK */
|
|
|
|
#if !defined(SPIN_DELAY)
|
|
#define SPIN_DELAY() ((void) 0)
|
|
#endif /* SPIN_DELAY */
|
|
|
|
#if !defined(TAS)
|
|
extern int tas(volatile slock_t *lock); /* in port/.../tas.s, or
|
|
* s_lock.c */
|
|
|
|
#define TAS(lock) tas(lock)
|
|
#endif /* TAS */
|
|
|
|
#if !defined(TAS_SPIN)
|
|
#define TAS_SPIN(lock) TAS(lock)
|
|
#endif /* TAS_SPIN */
|
|
|
|
extern slock_t dummy_spinlock;
|
|
|
|
/*
|
|
* Platform-independent out-of-line support routines
|
|
*/
|
|
extern int s_lock(volatile slock_t *lock, const char *file, int line, const char *func);
|
|
|
|
/* Support for dynamic adjustment of spins_per_delay */
|
|
#define DEFAULT_SPINS_PER_DELAY 100
|
|
|
|
extern void set_spins_per_delay(int shared_spins_per_delay);
|
|
extern int update_spins_per_delay(int shared_spins_per_delay);
|
|
|
|
/*
|
|
* Support for spin delay which is useful in various places where
|
|
* spinlock-like procedures take place.
|
|
*/
|
|
typedef struct
|
|
{
|
|
int spins;
|
|
int delays;
|
|
int cur_delay;
|
|
const char *file;
|
|
int line;
|
|
const char *func;
|
|
} SpinDelayStatus;
|
|
|
|
static inline void
|
|
init_spin_delay(SpinDelayStatus *status,
|
|
const char *file, int line, const char *func)
|
|
{
|
|
status->spins = 0;
|
|
status->delays = 0;
|
|
status->cur_delay = 0;
|
|
status->file = file;
|
|
status->line = line;
|
|
status->func = func;
|
|
}
|
|
|
|
#define init_local_spin_delay(status) init_spin_delay(status, __FILE__, __LINE__, PG_FUNCNAME_MACRO)
|
|
void perform_spin_delay(SpinDelayStatus *status);
|
|
void finish_spin_delay(SpinDelayStatus *status);
|
|
|
|
#endif /* S_LOCK_H */
|