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Merge pull request #494 from lioncash/shift
dyncom: Implement missing shifts in ScaledRegisterPostIndexed, etc
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commit
004b23153b
@ -410,10 +410,21 @@ void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, un
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}
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break;
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case 2:
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DEBUG_MSG;
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if (shift_imm == 0) { // ASR #32
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if (BIT(rm, 31) == 1)
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index = 0xFFFFFFFF;
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else
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index = 0;
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} else {
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index = static_cast<int>(rm) >> shift_imm;
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}
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break;
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case 3:
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DEBUG_MSG;
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if (shift_imm == 0) {
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index = (cpu->CFlag << 31) | (rm >> 1);
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} else {
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index = ROTATE_RIGHT_32(rm, shift_imm);
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}
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break;
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}
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@ -449,10 +460,21 @@ void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, u
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}
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break;
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case 2:
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DEBUG_MSG;
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if (shift_imm == 0) { // ASR #32
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if (BIT(rm, 31) == 1)
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index = 0xFFFFFFFF;
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else
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index = 0;
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} else {
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index = static_cast<int>(rm) >> shift_imm;
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}
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break;
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case 3:
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DEBUG_MSG;
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if (shift_imm == 0) {
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index = (cpu->CFlag << 31) | (rm >> 1);
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} else {
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index = ROTATE_RIGHT_32(rm, shift_imm);
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}
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break;
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}
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@ -655,7 +677,7 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign
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break;
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case 2:
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if (shift_imm == 0) { // ASR #32
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if (rm >> 31)
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if (BIT(rm, 31) == 1)
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index = 0xFFFFFFFF;
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else
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index = 0;
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@ -664,7 +686,11 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign
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}
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break;
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case 3:
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DEBUG_MSG;
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if (shift_imm == 0) {
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index = (cpu->CFlag << 31) | (rm >> 1);
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} else {
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index = ROTATE_RIGHT_32(rm, shift_imm);
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}
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break;
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}
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