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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-21 11:43:22 +02:00
dyncom: Implement USAT/SSAT
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parent
78bb86293f
commit
021fb42075
@ -1100,6 +1100,14 @@ typedef struct _smla_inst {
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unsigned int Rn;
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} smla_inst;
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typedef struct ssat_inst {
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unsigned int Rn;
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unsigned int Rd;
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unsigned int imm5;
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unsigned int sat_imm;
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unsigned int shift_type;
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} ssat_inst;
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typedef struct umaal_inst {
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unsigned int Rn;
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unsigned int Rm;
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@ -2525,7 +2533,24 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index)
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMUSD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSAT"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst));
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ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->Rn = BITS(inst, 0, 3);
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inst_cream->Rd = BITS(inst, 12, 15);
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inst_cream->imm5 = BITS(inst, 7, 11);
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inst_cream->sat_imm = BITS(inst, 16, 20);
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inst_cream->shift_type = BIT(inst, 6);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSAT16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SSUB8"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index)
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@ -3128,7 +3153,10 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(usada8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAT"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(ssat)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USAT16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USUB16"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("USUB8"); }
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@ -5514,6 +5542,38 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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SMUSD_INST:
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SRS_INST:
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SSAT_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
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u8 shift_type = inst_cream->shift_type;
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u8 shift_amount = inst_cream->imm5;
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u32 rn_val = RN;
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// 32-bit ASR is encoded as an amount of 0.
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if (shift_type == 1 && shift_amount == 0)
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shift_amount = 31;
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if (shift_type == 0)
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rn_val <<= shift_amount;
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else if (shift_type == 1)
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rn_val = ((s32)rn_val >> shift_amount);
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bool saturated = false;
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rn_val = ARMul_SignedSatQ(rn_val, inst_cream->sat_imm, &saturated);
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if (saturated)
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cpu->Cpsr |= (1 << 27);
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RD = rn_val;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ssat_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SSAT16_INST:
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SSUB8_INST:
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STC_INST:
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@ -6262,6 +6322,38 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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USAT_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
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u8 shift_type = inst_cream->shift_type;
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u8 shift_amount = inst_cream->imm5;
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u32 rn_val = RN;
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// 32-bit ASR is encoded as an amount of 0.
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if (shift_type == 1 && shift_amount == 0)
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shift_amount = 31;
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if (shift_type == 0)
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rn_val <<= shift_amount;
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else if (shift_type == 1)
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rn_val = ((s32)rn_val >> shift_amount);
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bool saturated = false;
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rn_val = ARMul_UnsignedSatQ(rn_val, inst_cream->sat_imm, &saturated);
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if (saturated)
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cpu->Cpsr |= (1 << 27);
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RD = rn_val;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(ssat_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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USAT16_INST:
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USUB16_INST:
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USUB8_INST:
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@ -578,6 +578,41 @@ u16 ARMul_UnsignedSaturatedSub16(u16 left, u16 right)
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return left - right;
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}
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// Signed saturation.
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u32 ARMul_SignedSatQ(s32 value, u8 shift, bool* saturation_occurred)
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{
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const u32 max = (1 << shift) - 1;
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const s32 top = (value >> shift);
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if (top > 0) {
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*saturation_occurred = true;
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return max;
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}
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else if (top < -1) {
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*saturation_occurred = true;
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return ~max;
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}
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*saturation_occurred = false;
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return (u32)value;
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}
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// Unsigned saturation
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u32 ARMul_UnsignedSatQ(s32 value, u8 shift, bool* saturation_occurred)
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{
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const u32 max = (1 << shift) - 1;
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if (value < 0) {
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*saturation_occurred = true;
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return 0;
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} else if ((u32)value > max) {
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*saturation_occurred = true;
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return max;
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}
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*saturation_occurred = false;
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return (u32)value;
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}
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/* This function does the work of generating the addresses used in an
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LDC instruction. The code here is always post-indexed, it's up to the
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@ -800,6 +800,8 @@ extern u16 ARMul_UnsignedSaturatedAdd16(u16, u16);
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extern u8 ARMul_UnsignedSaturatedSub8(u8, u8);
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extern u16 ARMul_UnsignedSaturatedSub16(u16, u16);
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extern u8 ARMul_UnsignedAbsoluteDifference(u8, u8);
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extern u32 ARMul_SignedSatQ(s32, u8, bool*);
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extern u32 ARMul_UnsignedSatQ(s32, u8, bool*);
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#define DIFF_LOG 0
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#define SAVE_LOG 0
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