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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-22 00:43:23 +02:00
fix for nvdec disabled, cleanup host1x
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parent
2c27127d04
commit
06cef3355e
@ -73,14 +73,15 @@ NvResult nvhost_nvdec_common::Submit(const std::vector<u8>& input, std::vector<u
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offset = SpliceVectors(input, wait_checks, params.syncpoint_count, offset);
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offset = SpliceVectors(input, fences, params.fence_count, offset);
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for (std::size_t i = 0; i < syncpt_increments.size(); i++) {
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SyncptIncr syncpt_incr = syncpt_increments[i];
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fences[i].id = syncpt_incr.id;
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fences[i].value =
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syncpoint_manager.IncreaseSyncpoint(syncpt_incr.id, syncpt_incr.increments);
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}
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auto& gpu = system.GPU();
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if (gpu.UseNvdec()) {
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for (std::size_t i = 0; i < syncpt_increments.size(); i++) {
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const SyncptIncr& syncpt_incr = syncpt_increments[i];
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fences[i].id = syncpt_incr.id;
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fences[i].value =
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syncpoint_manager.IncreaseSyncpoint(syncpt_incr.id, syncpt_incr.increments);
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}
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}
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for (const auto& cmd_buffer : command_buffers) {
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auto object = nvmap_dev->GetObject(cmd_buffer.memory_id);
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ASSERT_OR_EXECUTE(object, return NvResult::InvalidState;);
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@ -95,11 +96,13 @@ NvResult nvhost_nvdec_common::Submit(const std::vector<u8>& input, std::vector<u
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cmdlist.size() * sizeof(u32));
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gpu.PushCommandBuffer(cmdlist);
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}
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fences[0].value = syncpoint_manager.IncreaseSyncpoint(fences[0].id, 1);
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if (gpu.UseNvdec()) {
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Tegra::ChCommandHeaderList cmdlist{{(4 << 28) | fences[0].id}};
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gpu.PushCommandBuffer(cmdlist);
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fences[0].value = syncpoint_manager.IncreaseSyncpoint(fences[0].id, 1);
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Tegra::ChCommandHeaderList cmdlist{{(4 << 28) | fences[0].id}};
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gpu.PushCommandBuffer(cmdlist);
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}
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std::memcpy(output.data(), ¶ms, sizeof(IoctlSubmit));
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// Some games expect command_buffers to be written back
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offset = sizeof(IoctlSubmit);
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@ -118,7 +121,7 @@ NvResult nvhost_nvdec_common::GetSyncpoint(const std::vector<u8>& input, std::ve
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std::memcpy(¶ms, input.data(), sizeof(IoctlGetSyncpoint));
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LOG_DEBUG(Service_NVDRV, "called GetSyncpoint, id={}", params.param);
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if (device_syncpoints[params.param] == 0) {
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if (device_syncpoints[params.param] == 0 && system.GPU().UseNvdec()) {
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device_syncpoints[params.param] = syncpoint_manager.AllocateSyncpoint();
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}
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params.value = device_syncpoints[params.param];
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@ -10,22 +10,14 @@ Tegra::Host1x::Host1x(GPU& gpu_) : gpu(gpu_) {}
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Tegra::Host1x::~Host1x() = default;
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void Tegra::Host1x::StateWrite(u32 offset, u32 arguments) {
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u8* const state_offset = reinterpret_cast<u8*>(&state) + offset * sizeof(u32);
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std::memcpy(state_offset, &arguments, sizeof(u32));
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}
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void Tegra::Host1x::ProcessMethod(Method method, const std::vector<u32>& arguments) {
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StateWrite(static_cast<u32>(method), arguments[0]);
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void Tegra::Host1x::ProcessMethod(Method method, u32 argument) {
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switch (method) {
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case Method::WaitSyncpt:
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Execute(arguments[0]);
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break;
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case Method::LoadSyncptPayload32:
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syncpoint_value = arguments[0];
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syncpoint_value = argument;
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break;
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case Method::WaitSyncpt:
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case Method::WaitSyncpt32:
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Execute(arguments[0]);
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Execute(argument);
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break;
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default:
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UNIMPLEMENTED_MSG("Host1x method 0x{:X}", static_cast<u32>(method));
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@ -34,8 +26,5 @@ void Tegra::Host1x::ProcessMethod(Method method, const std::vector<u32>& argumen
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}
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void Tegra::Host1x::Execute(u32 data) {
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u32 syncpointId = (data & 0xFF);
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u32 threshold = state.load_syncpoint_payload32;
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gpu.WaitFence(syncpointId, threshold);
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gpu.WaitFence(data, syncpoint_value);
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}
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@ -14,64 +14,23 @@ class Nvdec;
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class Host1x {
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public:
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struct Host1xClassRegisters {
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u32 incr_syncpt{};
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u32 incr_syncpt_ctrl{};
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u32 incr_syncpt_error{};
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INSERT_PADDING_WORDS(5);
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u32 wait_syncpt{};
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u32 wait_syncpt_base{};
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u32 wait_syncpt_incr{};
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u32 load_syncpt_base{};
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u32 incr_syncpt_base{};
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u32 clear{};
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u32 wait{};
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u32 wait_with_interrupt{};
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u32 delay_use{};
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u32 tick_count_high{};
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u32 tick_count_low{};
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u32 tick_ctrl{};
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INSERT_PADDING_WORDS(23);
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u32 ind_ctrl{};
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u32 ind_off2{};
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u32 ind_off{};
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std::array<u32, 31> ind_data{};
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INSERT_PADDING_WORDS(1);
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u32 load_syncpoint_payload32{};
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u32 stall_ctrl{};
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u32 wait_syncpt32{};
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u32 wait_syncpt_base32{};
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u32 load_syncpt_base32{};
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u32 incr_syncpt_base32{};
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u32 stall_count_high{};
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u32 stall_count_low{};
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u32 xref_ctrl{};
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u32 channel_xref_high{};
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u32 channel_xref_low{};
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};
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static_assert(sizeof(Host1xClassRegisters) == 0x164, "Host1xClassRegisters is an invalid size");
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enum class Method : u32 {
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WaitSyncpt = offsetof(Host1xClassRegisters, wait_syncpt) / 4,
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LoadSyncptPayload32 = offsetof(Host1xClassRegisters, load_syncpoint_payload32) / 4,
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WaitSyncpt32 = offsetof(Host1xClassRegisters, wait_syncpt32) / 4,
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WaitSyncpt = 0x8,
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LoadSyncptPayload32 = 0x4e,
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WaitSyncpt32 = 0x50,
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};
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explicit Host1x(GPU& gpu);
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~Host1x();
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/// Writes the method into the state, Invoke Execute() if encountered
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void ProcessMethod(Method method, const std::vector<u32>& arguments);
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void ProcessMethod(Method method, u32 argument);
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private:
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/// For Host1x, execute is waiting on a syncpoint previously written into the state
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void Execute(u32 data);
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/// Write argument into the provided offset
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void StateWrite(u32 offset, u32 arguments);
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u32 syncpoint_value{};
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Host1xClassRegisters state{};
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GPU& gpu;
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};
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