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Merge pull request #379 from Subv/multi_buffers
GPU: Support multiple enabled vertex arrays.
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commit
07dc0bbf3e
@ -500,6 +500,11 @@ public:
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(start_high) << 32) |
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start_low);
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}
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bool IsEnabled() const {
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return enable != 0 && StartAddress() != 0;
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}
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} vertex_array[NumVertexArrays];
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Blend blend;
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@ -127,7 +127,8 @@ RasterizerOpenGL::~RasterizerOpenGL() {
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}
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}
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void RasterizerOpenGL::SetupVertexArray(u8* array_ptr, GLintptr buffer_offset) {
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std::pair<u8*, GLintptr> RasterizerOpenGL::SetupVertexArrays(u8* array_ptr,
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GLintptr buffer_offset) {
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MICROPROFILE_SCOPE(OpenGL_VAO);
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager;
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@ -136,43 +137,59 @@ void RasterizerOpenGL::SetupVertexArray(u8* array_ptr, GLintptr buffer_offset) {
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state.draw.vertex_buffer = stream_buffer->GetHandle();
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state.Apply();
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// TODO(bunnei): Add support for 1+ vertex arrays
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const auto& vertex_array{regs.vertex_array[0]};
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const auto& vertex_array_limit{regs.vertex_array_limit[0]};
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ASSERT_MSG(vertex_array.enable, "vertex array 0 is disabled?");
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ASSERT_MSG(!vertex_array.divisor, "vertex array 0 divisor is unimplemented!");
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for (unsigned index = 1; index < Maxwell::NumVertexArrays; ++index) {
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ASSERT_MSG(!regs.vertex_array[index].enable, "vertex array %d is unimplemented!", index);
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// Upload all guest vertex arrays sequentially to our buffer
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for (u32 index = 0; index < Maxwell::NumVertexArrays; ++index) {
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const auto& vertex_array = regs.vertex_array[index];
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if (!vertex_array.IsEnabled())
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continue;
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const Tegra::GPUVAddr start = vertex_array.StartAddress();
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const Tegra::GPUVAddr end = regs.vertex_array_limit[index].LimitAddress();
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ASSERT(end > start);
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u64 size = end - start + 1;
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// Copy vertex array data
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const VAddr data_addr{memory_manager->PhysicalToVirtualAddress(start)};
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res_cache.FlushRegion(data_addr, size, nullptr);
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Memory::ReadBlock(data_addr, array_ptr, size);
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// Bind the vertex array to the buffer at the current offset.
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glBindVertexBuffer(index, stream_buffer->GetHandle(), buffer_offset, vertex_array.stride);
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ASSERT_MSG(vertex_array.divisor == 0, "Vertex buffer divisor unimplemented");
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array_ptr += size;
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buffer_offset += size;
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}
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// Use the vertex array as-is, assumes that the data is formatted correctly for OpenGL.
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// Enables the first 16 vertex attributes always, as we don't know which ones are actually used
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// until shader time. Note, Tegra technically supports 32, but we're cappinig this to 16 for now
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// until shader time. Note, Tegra technically supports 32, but we're capping this to 16 for now
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// to avoid OpenGL errors.
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// TODO(Subv): Analyze the shader to identify which attributes are actually used and don't
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// assume every shader uses them all.
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for (unsigned index = 0; index < 16; ++index) {
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auto& attrib = regs.vertex_attrib_format[index];
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NGLOG_DEBUG(HW_GPU, "vertex attrib {}, count={}, size={}, type={}, offset={}, normalize={}",
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index, attrib.ComponentCount(), attrib.SizeString(), attrib.TypeString(),
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attrib.offset.Value(), attrib.IsNormalized());
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glVertexAttribPointer(index, attrib.ComponentCount(), MaxwellToGL::VertexType(attrib),
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attrib.IsNormalized() ? GL_TRUE : GL_FALSE, vertex_array.stride,
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reinterpret_cast<GLvoid*>(buffer_offset + attrib.offset));
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auto& buffer = regs.vertex_array[attrib.buffer];
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ASSERT(buffer.IsEnabled());
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glEnableVertexAttribArray(index);
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glVertexAttribFormat(index, attrib.ComponentCount(), MaxwellToGL::VertexType(attrib),
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attrib.IsNormalized() ? GL_TRUE : GL_FALSE, attrib.offset);
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glVertexAttribBinding(index, attrib.buffer);
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hw_vao_enabled_attributes[index] = true;
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}
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// Copy vertex array data
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const u64 data_size{vertex_array_limit.LimitAddress() - vertex_array.StartAddress() + 1};
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const VAddr data_addr{memory_manager->PhysicalToVirtualAddress(vertex_array.StartAddress())};
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res_cache.FlushRegion(data_addr, data_size, nullptr);
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Memory::ReadBlock(data_addr, array_ptr, data_size);
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array_ptr += data_size;
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buffer_offset += data_size;
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return {array_ptr, buffer_offset};
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}
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void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset, size_t ptr_pos) {
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void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset) {
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// Helper function for uploading uniform data
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const auto copy_buffer = [&](GLuint handle, GLintptr offset, GLsizeiptr size) {
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if (has_ARB_direct_state_access) {
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@ -190,8 +207,6 @@ void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset, size
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u32 current_constbuffer_bindpoint = 0;
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for (unsigned index = 1; index < Maxwell::MaxShaderProgram; ++index) {
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ptr_pos += sizeof(GLShader::MaxwellUniformData);
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auto& shader_config = gpu.regs.shader_config[index];
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const Maxwell::ShaderProgram program{static_cast<Maxwell::ShaderProgram>(index)};
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@ -205,13 +220,16 @@ void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset, size
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}
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// Upload uniform data as one UBO per stage
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const GLintptr ubo_offset = buffer_offset + static_cast<GLintptr>(ptr_pos);
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const GLintptr ubo_offset = buffer_offset;
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copy_buffer(uniform_buffers[stage].handle, ubo_offset,
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sizeof(GLShader::MaxwellUniformData));
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GLShader::MaxwellUniformData* ub_ptr =
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reinterpret_cast<GLShader::MaxwellUniformData*>(&buffer_ptr[ptr_pos]);
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reinterpret_cast<GLShader::MaxwellUniformData*>(buffer_ptr);
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ub_ptr->SetFromRegs(gpu.state.shader_stages[stage]);
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buffer_ptr += sizeof(GLShader::MaxwellUniformData);
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buffer_offset += sizeof(GLShader::MaxwellUniformData);
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// Fetch program code from memory
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GLShader::ProgramCode program_code;
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const u64 gpu_address{gpu.regs.code_address.CodeAddress() + shader_config.offset};
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@ -252,6 +270,24 @@ void RasterizerOpenGL::SetupShaders(u8* buffer_ptr, GLintptr buffer_offset, size
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shader_program_manager->UseTrivialGeometryShader();
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}
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size_t RasterizerOpenGL::CalculateVertexArraysSize() const {
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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size_t size = 0;
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for (u32 index = 0; index < Maxwell::NumVertexArrays; ++index) {
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if (!regs.vertex_array[index].IsEnabled())
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continue;
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const Tegra::GPUVAddr start = regs.vertex_array[index].StartAddress();
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const Tegra::GPUVAddr end = regs.vertex_array_limit[index].LimitAddress();
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ASSERT(end > start);
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size += end - start + 1;
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}
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return size;
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}
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bool RasterizerOpenGL::AccelerateDrawBatch(bool is_indexed) {
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accelerate_draw = is_indexed ? AccelDraw::Indexed : AccelDraw::Arrays;
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DrawArrays();
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@ -329,44 +365,49 @@ void RasterizerOpenGL::DrawArrays() {
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const u64 index_buffer_size{regs.index_array.count * regs.index_array.FormatSizeInBytes()};
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const unsigned vertex_num{is_indexed ? regs.index_array.count : regs.vertex_buffer.count};
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// TODO(bunnei): Add support for 1+ vertex arrays
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vs_input_size = vertex_num * regs.vertex_array[0].stride;
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state.draw.vertex_buffer = stream_buffer->GetHandle();
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state.Apply();
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size_t buffer_size = static_cast<size_t>(vs_input_size);
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size_t buffer_size = CalculateVertexArraysSize();
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if (is_indexed) {
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buffer_size = Common::AlignUp(buffer_size, 4) + index_buffer_size;
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buffer_size = Common::AlignUp<size_t>(buffer_size, 4) + index_buffer_size;
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}
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// Uniform space for the 5 shader stages
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buffer_size += sizeof(GLShader::MaxwellUniformData) * Maxwell::MaxShaderStage;
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buffer_size = Common::AlignUp<size_t>(buffer_size, 4) +
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sizeof(GLShader::MaxwellUniformData) * Maxwell::MaxShaderStage;
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size_t ptr_pos = 0;
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u8* buffer_ptr;
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GLintptr buffer_offset;
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std::tie(buffer_ptr, buffer_offset) =
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stream_buffer->Map(static_cast<GLsizeiptr>(buffer_size), 4);
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SetupVertexArray(buffer_ptr, buffer_offset);
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ptr_pos += vs_input_size;
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u8* offseted_buffer;
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std::tie(offseted_buffer, buffer_offset) = SetupVertexArrays(buffer_ptr, buffer_offset);
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offseted_buffer =
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reinterpret_cast<u8*>(Common::AlignUp(reinterpret_cast<size_t>(offseted_buffer), 4));
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buffer_offset = Common::AlignUp<size_t>(buffer_offset, 4);
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// If indexed mode, copy the index buffer
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GLintptr index_buffer_offset = 0;
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if (is_indexed) {
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ptr_pos = Common::AlignUp(ptr_pos, 4);
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const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager;
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const VAddr index_data_addr{
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memory_manager->PhysicalToVirtualAddress(regs.index_array.StartAddress())};
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Memory::ReadBlock(index_data_addr, &buffer_ptr[ptr_pos], index_buffer_size);
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Memory::ReadBlock(index_data_addr, offseted_buffer, index_buffer_size);
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index_buffer_offset = buffer_offset + static_cast<GLintptr>(ptr_pos);
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ptr_pos += index_buffer_size;
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index_buffer_offset = buffer_offset;
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offseted_buffer += index_buffer_size;
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buffer_offset += index_buffer_size;
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}
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SetupShaders(buffer_ptr, buffer_offset, ptr_pos);
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offseted_buffer =
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reinterpret_cast<u8*>(Common::AlignUp(reinterpret_cast<size_t>(offseted_buffer), 4));
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buffer_offset = Common::AlignUp<size_t>(buffer_offset, 4);
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SetupShaders(offseted_buffer, buffer_offset);
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stream_buffer->Unmap();
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@ -148,13 +148,13 @@ private:
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static constexpr size_t STREAM_BUFFER_SIZE = 4 * 1024 * 1024;
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std::unique_ptr<OGLStreamBuffer> stream_buffer;
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GLsizeiptr vs_input_size;
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size_t CalculateVertexArraysSize() const;
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void SetupVertexArray(u8* array_ptr, GLintptr buffer_offset);
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std::pair<u8*, GLintptr> SetupVertexArrays(u8* array_ptr, GLintptr buffer_offset);
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std::array<OGLBuffer, Tegra::Engines::Maxwell3D::Regs::MaxShaderStage> uniform_buffers;
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void SetupShaders(u8* buffer_ptr, GLintptr buffer_offset, size_t ptr_pos);
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void SetupShaders(u8* buffer_ptr, GLintptr buffer_offset);
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enum class AccelDraw { Disabled, Arrays, Indexed };
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AccelDraw accelerate_draw;
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