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surface: Correct format S8Z24
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03d489dcf5
commit
082740d34d
@ -111,7 +111,7 @@ void MaxwellDMA::HandleCopy() {
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memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
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memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
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} else {
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} else {
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ASSERT(regs.dst_params.BlockDepth() == 1);
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ASSERT(regs.dst_params.BlockDepth() == 0);
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const u32 src_bytes_per_pixel = regs.src_pitch / regs.x_count;
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const u32 src_bytes_per_pixel = regs.src_pitch / regs.x_count;
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@ -308,8 +308,8 @@ PixelFormat PixelFormatFromTextureFormat(Tegra::Texture::TextureFormat format,
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return PixelFormat::Z32F;
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return PixelFormat::Z32F;
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case Tegra::Texture::TextureFormat::Z16:
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case Tegra::Texture::TextureFormat::Z16:
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return PixelFormat::Z16;
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return PixelFormat::Z16;
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case Tegra::Texture::TextureFormat::Z24S8:
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case Tegra::Texture::TextureFormat::S8Z24:
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return PixelFormat::Z24S8;
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return PixelFormat::S8Z24;
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case Tegra::Texture::TextureFormat::ZF32_X24S8:
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case Tegra::Texture::TextureFormat::ZF32_X24S8:
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return PixelFormat::Z32FS8;
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return PixelFormat::Z32FS8;
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case Tegra::Texture::TextureFormat::DXT1:
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case Tegra::Texture::TextureFormat::DXT1:
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@ -534,10 +534,6 @@ private:
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const auto host_ptr{memory_manager->GetPointer(gpu_addr)};
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const auto host_ptr{memory_manager->GetPointer(gpu_addr)};
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const auto cache_addr{ToCacheAddr(host_ptr)};
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const auto cache_addr{ToCacheAddr(host_ptr)};
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if (gpu_addr == 0x00000001682F0000ULL) {
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LOG_CRITICAL(HW_GPU, "Here's the texture!");
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}
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// Step 0: guarantee a valid surface
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// Step 0: guarantee a valid surface
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if (!cache_addr) {
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if (!cache_addr) {
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// Return a null surface if it's invalid
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// Return a null surface if it's invalid
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@ -52,9 +52,9 @@ enum class TextureFormat : u32 {
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DXT45 = 0x26,
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DXT45 = 0x26,
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DXN1 = 0x27,
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DXN1 = 0x27,
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DXN2 = 0x28,
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DXN2 = 0x28,
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Z24S8 = 0x29,
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S8Z24 = 0x29,
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X8Z24 = 0x2a,
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X8Z24 = 0x2a,
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S8Z24 = 0x2b,
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Z24S8 = 0x2b,
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X4V4Z24__COV4R4V = 0x2c,
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X4V4Z24__COV4R4V = 0x2c,
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X4V4Z24__COV8R8V = 0x2d,
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X4V4Z24__COV8R8V = 0x2d,
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V8Z24__COV4R12V = 0x2e,
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V8Z24__COV4R12V = 0x2e,
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