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Merge pull request #342 from bunnei/indexed-verts
Implement indexed mode rendering
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commit
0905dc1ff4
@ -165,6 +165,7 @@ void Maxwell3D::ProcessQueryGet() {
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void Maxwell3D::DrawArrays() {
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LOG_DEBUG(HW_GPU, "called, topology=%d, count=%d", regs.draw.topology.Value(),
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regs.vertex_buffer.count);
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ASSERT_MSG(!(regs.index_array.count && regs.vertex_buffer.count), "Both indexed and direct?");
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auto debug_context = Core::System::GetInstance().GetGPUDebugContext();
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@ -176,7 +177,8 @@ void Maxwell3D::DrawArrays() {
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debug_context->OnEvent(Tegra::DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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}
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VideoCore::g_renderer->Rasterizer()->AccelerateDrawBatch(false /*is_indexed*/);
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const bool is_indexed{regs.index_array.count && !regs.vertex_buffer.count};
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VideoCore::g_renderer->Rasterizer()->AccelerateDrawBatch(is_indexed);
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}
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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@ -248,6 +248,12 @@ public:
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Patches = 0xe,
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};
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enum class IndexFormat : u32 {
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UnsignedByte = 0x0,
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UnsignedShort = 0x1,
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UnsignedInt = 0x2,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0x200);
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@ -375,7 +381,42 @@ public:
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};
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} draw;
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INSERT_PADDING_WORDS(0x139);
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INSERT_PADDING_WORDS(0x6B);
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struct {
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u32 start_addr_high;
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u32 start_addr_low;
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u32 end_addr_high;
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u32 end_addr_low;
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IndexFormat format;
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u32 first;
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u32 count;
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unsigned FormatSizeInBytes() const {
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switch (format) {
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case IndexFormat::UnsignedByte:
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return 1;
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case IndexFormat::UnsignedShort:
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return 2;
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case IndexFormat::UnsignedInt:
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return 4;
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}
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UNREACHABLE();
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}
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GPUVAddr StartAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(start_addr_high) << 32) | start_addr_low);
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}
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GPUVAddr EndAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(end_addr_high) << 32) |
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end_addr_low);
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}
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} index_array;
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INSERT_PADDING_WORDS(0xC7);
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struct {
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u32 query_address_high;
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u32 query_address_low;
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@ -572,6 +613,7 @@ ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(code_address, 0x582);
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ASSERT_REG_POSITION(draw, 0x585);
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ASSERT_REG_POSITION(index_array, 0x5F2);
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ASSERT_REG_POSITION(query, 0x6C0);
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ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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@ -97,7 +97,6 @@ RasterizerOpenGL::RasterizerOpenGL() {
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state.draw.vertex_buffer = stream_buffer->GetHandle();
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shader_program_manager = std::make_unique<GLShader::ProgramManager>();
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state.draw.shader_program = 0;
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state.draw.vertex_array = hw_vao.handle;
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state.Apply();
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@ -128,17 +127,6 @@ RasterizerOpenGL::~RasterizerOpenGL() {
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}
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}
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void RasterizerOpenGL::AnalyzeVertexArray(bool is_indexed) {
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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if (is_indexed) {
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UNREACHABLE();
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}
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// TODO(bunnei): Add support for 1+ vertex arrays
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vs_input_size = regs.vertex_buffer.count * regs.vertex_array[0].stride;
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}
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void RasterizerOpenGL::SetupVertexArray(u8* array_ptr, GLintptr buffer_offset) {
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MICROPROFILE_SCOPE(OpenGL_VAO);
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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@ -150,6 +138,7 @@ void RasterizerOpenGL::SetupVertexArray(u8* array_ptr, GLintptr buffer_offset) {
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// TODO(bunnei): Add support for 1+ vertex arrays
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const auto& vertex_array{regs.vertex_array[0]};
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const auto& vertex_array_limit{regs.vertex_array_limit[0]};
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ASSERT_MSG(vertex_array.enable, "vertex array 0 is disabled?");
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ASSERT_MSG(!vertex_array.divisor, "vertex array 0 divisor is unimplemented!");
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for (unsigned index = 1; index < Maxwell::NumVertexArrays; ++index) {
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@ -162,6 +151,10 @@ void RasterizerOpenGL::SetupVertexArray(u8* array_ptr, GLintptr buffer_offset) {
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// to avoid OpenGL errors.
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for (unsigned index = 0; index < 16; ++index) {
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auto& attrib = regs.vertex_attrib_format[index];
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NGLOG_DEBUG(HW_GPU, "vertex attrib {}, count={}, size={}, type={}, offset={}, normalize={}",
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index, attrib.ComponentCount(), attrib.SizeString(), attrib.TypeString(),
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attrib.offset.Value(), attrib.IsNormalized());
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glVertexAttribPointer(index, attrib.ComponentCount(), MaxwellToGL::VertexType(attrib),
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attrib.IsNormalized() ? GL_TRUE : GL_FALSE, vertex_array.stride,
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reinterpret_cast<GLvoid*>(buffer_offset + attrib.offset));
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@ -170,7 +163,7 @@ void RasterizerOpenGL::SetupVertexArray(u8* array_ptr, GLintptr buffer_offset) {
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}
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// Copy vertex array data
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const u32 data_size{vertex_array.stride * regs.vertex_buffer.count};
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const u64 data_size{vertex_array_limit.LimitAddress() - vertex_array.StartAddress() + 1};
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const VAddr data_addr{memory_manager->PhysicalToVirtualAddress(vertex_array.StartAddress())};
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res_cache.FlushRegion(data_addr, data_size, nullptr);
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Memory::ReadBlock(data_addr, array_ptr, data_size);
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@ -333,13 +326,18 @@ void RasterizerOpenGL::DrawArrays() {
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// Draw the vertex batch
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const bool is_indexed = accelerate_draw == AccelDraw::Indexed;
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AnalyzeVertexArray(is_indexed);
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const u64 index_buffer_size{regs.index_array.count * regs.index_array.FormatSizeInBytes()};
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const unsigned vertex_num{is_indexed ? regs.index_array.count : regs.vertex_buffer.count};
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// TODO(bunnei): Add support for 1+ vertex arrays
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vs_input_size = vertex_num * regs.vertex_array[0].stride;
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state.draw.vertex_buffer = stream_buffer->GetHandle();
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state.Apply();
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size_t buffer_size = static_cast<size_t>(vs_input_size);
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if (is_indexed) {
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UNREACHABLE();
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buffer_size = Common::AlignUp(buffer_size, 4) + index_buffer_size;
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}
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// Uniform space for the 5 shader stages
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@ -354,9 +352,18 @@ void RasterizerOpenGL::DrawArrays() {
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SetupVertexArray(buffer_ptr, buffer_offset);
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ptr_pos += vs_input_size;
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// If indexed mode, copy the index buffer
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GLintptr index_buffer_offset = 0;
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if (is_indexed) {
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UNREACHABLE();
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ptr_pos = Common::AlignUp(ptr_pos, 4);
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const auto& memory_manager = Core::System().GetInstance().GPU().memory_manager;
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const VAddr index_data_addr{
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memory_manager->PhysicalToVirtualAddress(regs.index_array.StartAddress())};
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Memory::ReadBlock(index_data_addr, &buffer_ptr[ptr_pos], index_buffer_size);
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index_buffer_offset = buffer_offset + static_cast<GLintptr>(ptr_pos);
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ptr_pos += index_buffer_size;
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}
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SetupShaders(buffer_ptr, buffer_offset, ptr_pos);
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@ -366,11 +373,16 @@ void RasterizerOpenGL::DrawArrays() {
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shader_program_manager->ApplyTo(state);
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state.Apply();
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const GLenum primitive_mode{MaxwellToGL::PrimitiveTopology(regs.draw.topology)};
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if (is_indexed) {
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UNREACHABLE();
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const GLint index_min{static_cast<GLint>(regs.index_array.first)};
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const GLint index_max{static_cast<GLint>(regs.index_array.first + regs.index_array.count)};
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glDrawRangeElementsBaseVertex(primitive_mode, index_min, index_max, regs.index_array.count,
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MaxwellToGL::IndexFormat(regs.index_array.format),
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reinterpret_cast<const void*>(index_buffer_offset),
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-index_min);
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} else {
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glDrawArrays(MaxwellToGL::PrimitiveTopology(regs.draw.topology), 0,
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regs.vertex_buffer.count);
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glDrawArrays(primitive_mode, 0, regs.vertex_buffer.count);
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}
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// Disable scissor test
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@ -155,7 +155,6 @@ private:
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GLsizeiptr vs_input_size;
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void AnalyzeVertexArray(bool is_indexed);
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void SetupVertexArray(u8* array_ptr, GLintptr buffer_offset);
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std::array<OGLBuffer, Tegra::Engines::Maxwell3D::Regs::MaxShaderStage> uniform_buffers;
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@ -31,7 +31,7 @@ inline GLenum VertexType(Maxwell::VertexAttribute attrib) {
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return GL_UNSIGNED_BYTE;
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}
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LOG_CRITICAL(Render_OpenGL, "Unimplemented vertex size=%s", attrib.SizeString().c_str());
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NGLOG_CRITICAL(Render_OpenGL, "Unimplemented vertex size={}", attrib.SizeString());
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UNREACHABLE();
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return {};
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}
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@ -40,7 +40,21 @@ inline GLenum VertexType(Maxwell::VertexAttribute attrib) {
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return GL_FLOAT;
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}
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LOG_CRITICAL(Render_OpenGL, "Unimplemented vertex type=%s", attrib.TypeString().c_str());
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NGLOG_CRITICAL(Render_OpenGL, "Unimplemented vertex type={}", attrib.TypeString());
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UNREACHABLE();
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return {};
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}
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inline GLenum IndexFormat(Maxwell::IndexFormat index_format) {
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switch (index_format) {
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case Maxwell::IndexFormat::UnsignedByte:
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return GL_UNSIGNED_BYTE;
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case Maxwell::IndexFormat::UnsignedShort:
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return GL_UNSIGNED_SHORT;
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case Maxwell::IndexFormat::UnsignedInt:
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return GL_UNSIGNED_INT;
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}
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NGLOG_CRITICAL(Render_OpenGL, "Unimplemented index_format={}", static_cast<u32>(index_format));
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UNREACHABLE();
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return {};
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}
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@ -52,7 +66,7 @@ inline GLenum PrimitiveTopology(Maxwell::PrimitiveTopology topology) {
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case Maxwell::PrimitiveTopology::TriangleStrip:
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return GL_TRIANGLE_STRIP;
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}
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LOG_CRITICAL(Render_OpenGL, "Unimplemented primitive topology=%d", topology);
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NGLOG_CRITICAL(Render_OpenGL, "Unimplemented topology={}", static_cast<u32>(topology));
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UNREACHABLE();
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return {};
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}
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@ -64,8 +78,8 @@ inline GLenum TextureFilterMode(Tegra::Texture::TextureFilter filter_mode) {
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case Tegra::Texture::TextureFilter::Nearest:
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return GL_NEAREST;
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}
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LOG_CRITICAL(Render_OpenGL, "Unimplemented texture filter mode=%u",
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static_cast<u32>(filter_mode));
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NGLOG_CRITICAL(Render_OpenGL, "Unimplemented texture filter mode={}",
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static_cast<u32>(filter_mode));
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UNREACHABLE();
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return {};
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}
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@ -75,7 +89,8 @@ inline GLenum WrapMode(Tegra::Texture::WrapMode wrap_mode) {
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case Tegra::Texture::WrapMode::ClampToEdge:
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return GL_CLAMP_TO_EDGE;
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}
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LOG_CRITICAL(Render_OpenGL, "Unimplemented texture wrap mode=%u", static_cast<u32>(wrap_mode));
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NGLOG_CRITICAL(Render_OpenGL, "Unimplemented texture wrap mode={}",
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static_cast<u32>(wrap_mode));
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UNREACHABLE();
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return {};
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}
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