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shader: Document and relax cache control on surface instructions
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@ -61,18 +61,19 @@ enum class Clamp : u64 {
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TRAP,
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#cache-operators
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enum class LoadCache : u64 {
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Default,
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CG,
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CI,
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CV,
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CA, // Cache at all levels, likely to be accessed again
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CG, // Cache at global level (L2 and below, not L1)
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CI, // ???
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CV, // Don't cache and fetch again (volatile)
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};
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enum class StoreCache : u64 {
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Default,
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CG,
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CS,
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WT,
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WB, // Cache write-back all coherent levels
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CG, // Cache at global level (L2 and below, not L1)
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CS, // Cache streaming, likely to be accessed once
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WT, // Cache write-through (to system memory, volatile?)
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};
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ImageFormat Format(Size size) {
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@ -188,7 +189,7 @@ void TranslatorVisitor::SULD(u64 insn) {
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if (suld.clamp != Clamp::IGN) {
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throw NotImplementedException("Clamp {}", suld.clamp.Value());
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}
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if (suld.cache != LoadCache::Default) {
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if (suld.cache != LoadCache::CA && suld.cache != LoadCache::CG) {
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throw NotImplementedException("Cache {}", suld.cache.Value());
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}
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const bool is_typed{suld.d != 0};
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@ -248,7 +249,7 @@ void TranslatorVisitor::SUST(u64 insn) {
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if (sust.clamp != Clamp::IGN) {
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throw NotImplementedException("Clamp {}", sust.clamp.Value());
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}
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if (sust.cache != StoreCache::Default) {
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if (sust.cache != StoreCache::WB && sust.cache != StoreCache::CG) {
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throw NotImplementedException("Cache {}", sust.cache.Value());
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}
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const bool is_typed{sust.d != 0};
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