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shader: ISET.X implementation
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@ -9,7 +9,56 @@
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namespace Shader::Maxwell {
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namespace {
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void ISET(TranslatorVisitor& v, u64 insn, const IR::U32& src_a) {
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IR::U1 ExtendedIntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed) {
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const IR::U32 zero{ir.Imm32(0)};
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const IR::U32 carry{ir.Select(ir.GetCFlag(), ir.Imm32(1), zero)};
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const IR::U1 z_flag{ir.GetZFlag()};
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const IR::U32 intermediate{ir.IAdd(ir.IAdd(operand_1, ir.BitwiseNot(operand_2)), carry)};
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const IR::U1 flip_logic{is_signed ? ir.Imm1(false)
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: ir.LogicalXor(ir.ILessThan(operand_1, zero, true),
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ir.ILessThan(operand_2, zero, true))};
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switch (compare_op) {
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case CompareOp::False:
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return ir.Imm1(false);
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case CompareOp::LessThan:
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return IR::U1{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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case CompareOp::Equal:
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return ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag);
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case CompareOp::LessThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.IGreaterThanEqual(intermediate, zero, true),
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ir.ILessThan(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::GreaterThan: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThanEqual(intermediate, zero, true),
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ir.IGreaterThan(intermediate, zero, true))};
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const IR::U1 not_z{ir.LogicalNot(z_flag)};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), not_z));
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}
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case CompareOp::NotEqual:
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return ir.LogicalOr(ir.INotEqual(intermediate, zero),
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ir.LogicalAnd(ir.IEqual(intermediate, zero), ir.LogicalNot(z_flag)));
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case CompareOp::GreaterThanEqual: {
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const IR::U1 base_cmp{ir.Select(flip_logic, ir.ILessThan(intermediate, zero, true),
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ir.IGreaterThanEqual(intermediate, zero, true))};
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return ir.LogicalOr(base_cmp, ir.LogicalAnd(ir.IEqual(intermediate, zero), z_flag));
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}
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case CompareOp::True:
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return ir.Imm1(true);
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default:
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throw NotImplementedException("Invalid compare op {}", compare_op);
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}
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}
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IR::U1 IsetCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed, bool x) {
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return x ? ExtendedIntegerCompare(ir, operand_1, operand_2, compare_op, is_signed)
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: IntegerCompare(ir, operand_1, operand_2, compare_op, is_signed);
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}
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void ISET(TranslatorVisitor& v, u64 insn, const IR::U32& src_b) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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@ -24,27 +73,28 @@ void ISET(TranslatorVisitor& v, u64 insn, const IR::U32& src_a) {
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BitField<49, 3, CompareOp> compare_op;
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} const iset{insn};
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if (iset.x != 0) {
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throw NotImplementedException("ISET.X");
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}
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const IR::U32 src_reg{v.X(iset.src_reg)};
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const IR::U32 src_a{v.X(iset.src_reg)};
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const bool is_signed{iset.is_signed != 0};
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const IR::U32 zero{v.ir.Imm32(0)};
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const bool x{iset.x != 0};
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const IR::U1 cmp_result{IsetCompare(v.ir, src_a, src_b, iset.compare_op, is_signed, x)};
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IR::U1 pred{v.ir.GetPred(iset.pred)};
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if (iset.neg_pred != 0) {
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pred = v.ir.LogicalNot(pred);
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}
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const IR::U1 cmp_result{IntegerCompare(v.ir, src_reg, src_a, iset.compare_op, is_signed)};
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const IR::U1 bop_result{PredicateCombine(v.ir, cmp_result, pred, iset.bop)};
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const IR::U32 one_mask{v.ir.Imm32(-1)};
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const IR::U32 fp_one{v.ir.Imm32(0x3f800000)};
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const IR::U32 zero{v.ir.Imm32(0)};
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const IR::U32 pass_result{iset.bf == 0 ? one_mask : fp_one};
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const IR::U32 result{v.ir.Select(bop_result, pass_result, zero)};
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v.X(iset.dest_reg, result);
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if (iset.cc != 0) {
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if (x) {
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throw NotImplementedException("ISET.CC + X");
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}
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const IR::U1 is_zero{v.ir.IEqual(result, zero)};
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v.SetZFlag(is_zero);
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if (iset.bf != 0) {
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