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https://github.com/yuzu-emu/yuzu.git
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arm_disasm: ARMv6 reversal media instructions
REV, REV16, REVSH Only their ARM encoding, Thumb encoding is still missing.
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e4ff244288
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@ -69,6 +69,9 @@ static const char *opcode_names[] = {
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"orr",
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"orr",
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"pkh",
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"pkh",
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"pld",
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"pld",
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"rev",
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"rev16",
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"revsh",
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"rsb",
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"rsb",
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"rsc",
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"rsc",
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"sbc",
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"sbc",
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@ -259,6 +262,10 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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return DisassemblePKH(insn);
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return DisassemblePKH(insn);
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case OP_PLD:
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case OP_PLD:
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return DisassemblePLD(insn);
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return DisassemblePLD(insn);
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case OP_REV:
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case OP_REV16:
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case OP_REVSH:
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return DisassembleREV(opcode, insn);
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case OP_SEL:
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case OP_SEL:
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return DisassembleSEL(insn);
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return DisassembleSEL(insn);
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case OP_SSAT:
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case OP_SSAT:
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@ -772,6 +779,15 @@ std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
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}
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}
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}
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}
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std::string ARM_Disasm::DisassembleREV(Opcode opcode, uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 0, 3);
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return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond),
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rd, rm);
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}
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std::string ARM_Disasm::DisassembleREX(Opcode opcode, uint32_t insn) {
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std::string ARM_Disasm::DisassembleREX(Opcode opcode, uint32_t insn) {
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rd = BITS(insn, 12, 15);
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@ -1094,12 +1110,16 @@ Opcode ARM_Disasm::DecodePackingSaturationReversal(uint32_t insn) {
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return OP_SXTB;
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return OP_SXTB;
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break;
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break;
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case 0x3:
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case 0x3:
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if (op2 == 0x1)
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return OP_REV;
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if (BIT(op2, 0) == 0)
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if (BIT(op2, 0) == 0)
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return OP_SSAT;
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return OP_SSAT;
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if (op2 == 0x3 && a != 0xf)
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if (op2 == 0x3 && a != 0xf)
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return OP_SXTAH;
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return OP_SXTAH;
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if (op2 == 0x3 && a == 0xf)
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if (op2 == 0x3 && a == 0xf)
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return OP_SXTH;
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return OP_SXTH;
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if (op2 == 0x5)
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return OP_REV16;
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break;
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break;
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case 0x4:
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case 0x4:
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if (op2 == 0x3 && a != 0xf)
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if (op2 == 0x3 && a != 0xf)
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@ -1124,6 +1144,8 @@ Opcode ARM_Disasm::DecodePackingSaturationReversal(uint32_t insn) {
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return OP_UXTAH;
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return OP_UXTAH;
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if (op2 == 0x3 && a == 0xf)
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if (op2 == 0x3 && a == 0xf)
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return OP_UXTH;
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return OP_UXTH;
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if (op2 == 0x5)
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return OP_REVSH;
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break;
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break;
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default:
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default:
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break;
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break;
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@ -50,6 +50,9 @@ enum Opcode {
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OP_ORR,
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OP_ORR,
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OP_PKH,
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OP_PKH,
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OP_PLD,
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OP_PLD,
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OP_REV,
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OP_REV16,
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OP_REVSH,
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OP_RSB,
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OP_RSB,
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OP_RSC,
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OP_RSC,
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OP_SBC,
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OP_SBC,
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@ -174,6 +177,7 @@ class ARM_Disasm {
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static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
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static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
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static std::string DisassemblePKH(uint32_t insn);
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static std::string DisassemblePKH(uint32_t insn);
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static std::string DisassemblePLD(uint32_t insn);
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static std::string DisassemblePLD(uint32_t insn);
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static std::string DisassembleREV(Opcode opcode, uint32_t insn);
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static std::string DisassembleREX(Opcode opcode, uint32_t insn);
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static std::string DisassembleREX(Opcode opcode, uint32_t insn);
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static std::string DisassembleSAT(Opcode opcode, uint32_t insn);
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static std::string DisassembleSAT(Opcode opcode, uint32_t insn);
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static std::string DisassembleSEL(uint32_t insn);
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static std::string DisassembleSEL(uint32_t insn);
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