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GPU: Properly implement memory fills.
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parent
745b42d236
commit
0da6a7e234
@ -368,28 +368,28 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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case CommandId::SET_MEMORY_FILL:
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{
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auto& params = command.memory_fill;
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_start)),
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Memory::VirtualToPhysicalAddress(params.start1) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_end)),
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Memory::VirtualToPhysicalAddress(params.end1) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].size)), params.end1 - params.start1);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value)), params.value1);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_start)),
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Memory::VirtualToPhysicalAddress(params.start1) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_end)),
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Memory::VirtualToPhysicalAddress(params.end1) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value_32bit)), params.value1);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].control)), params.control1);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_start)),
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Memory::VirtualToPhysicalAddress(params.start2) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_end)),
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Memory::VirtualToPhysicalAddress(params.end2) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].size)), params.end2 - params.start2);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value)), params.value2);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_start)),
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Memory::VirtualToPhysicalAddress(params.start2) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_end)),
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Memory::VirtualToPhysicalAddress(params.end2) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value_32bit)), params.value2);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].control)), params.control2);
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break;
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}
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case CommandId::SET_DISPLAY_TRANSFER:
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{
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auto& params = command.image_copy;
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
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Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
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Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size);
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@ -402,9 +402,9 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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case CommandId::SET_TEXTURE_COPY:
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{
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auto& params = command.image_copy;
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
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Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
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Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size);
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@ -109,9 +109,13 @@ struct Command {
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u32 start1;
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u32 value1;
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u32 end1;
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u32 start2;
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u32 value2;
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u32 end2;
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u16 control1;
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u16 control2;
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} memory_fill;
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struct {
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@ -67,23 +67,38 @@ inline void Write(u32 addr, const T data) {
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switch (index) {
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// Memory fills are triggered once the fill value is written.
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// NOTE: This is not verified.
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].value, 0x00004 + 0x3):
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].value, 0x00008 + 0x3):
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3):
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case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3):
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{
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const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].value));
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const auto& config = g_regs.memory_fill_config[is_second_filler];
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const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger));
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auto& config = g_regs.memory_fill_config[is_second_filler];
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// TODO: Not sure if this check should be done at GSP level instead
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if (config.address_start) {
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// TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
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u32* start = (u32*)Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetStartAddress()));
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u32* end = (u32*)Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetEndAddress()));
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for (u32* ptr = start; ptr < end; ++ptr)
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*ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
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if (config.address_start && config.trigger) {
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u8* start = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetStartAddress()));
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u8* end = Memory::GetPointer(Memory::PhysicalToVirtualAddress(config.GetEndAddress()));
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if (config.fill_24bit) {
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// fill with 24-bit values
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for (u8* ptr = start; ptr < end; ptr += 3) {
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ptr[0] = config.value_24bit_b;
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ptr[1] = config.value_24bit_g;
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ptr[2] = config.value_24bit_r;
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}
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} else if (config.fill_32bit) {
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// fill with 32-bit values
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for (u32* ptr = (u32*)start; ptr < (u32*)end; ++ptr)
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*ptr = config.value_32bit;
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} else {
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// fill with 16-bit values
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for (u16* ptr = (u16*)start; ptr < (u16*)end; ++ptr)
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*ptr = config.value_16bit;
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}
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LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress());
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config.trigger = 0;
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config.finished = 1;
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if (!is_second_filler) {
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GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0);
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} else {
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@ -84,9 +84,35 @@ struct Regs {
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struct {
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u32 address_start;
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u32 address_end; // ?
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u32 size;
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u32 value; // ?
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u32 address_end;
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union {
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u32 value_32bit;
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BitField<0, 16, u32> value_16bit;
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// TODO: Verify component order
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BitField< 0, 8, u32> value_24bit_r;
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BitField< 8, 8, u32> value_24bit_g;
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BitField<16, 8, u32> value_24bit_b;
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};
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union {
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u32 control;
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// Setting this field to 1 triggers the memory fill.
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// This field also acts as a status flag, and gets reset to 0 upon completion.
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BitField<0, 1, u32> trigger;
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// Set to 1 upon completion.
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BitField<0, 1, u32> finished;
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// 0: fill with 16- or 32-bit wide values; 1: fill with 24-bit wide values
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BitField<8, 1, u32> fill_24bit;
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// 0: fill with 16-bit wide values; 1: fill with 32-bit wide values
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BitField<9, 1, u32> fill_32bit;
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};
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inline u32 GetStartAddress() const {
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return DecodeAddressRegister(address_start);
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