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shader: Implement AL2P
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@ -65,6 +65,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/program.h
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frontend/maxwell/structured_control_flow.cpp
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frontend/maxwell/structured_control_flow.h
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frontend/maxwell/translate/impl/attribute_memory_to_physical.cpp
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frontend/maxwell/translate/impl/barrier_operations.cpp
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frontend/maxwell/translate/impl/bitfield_extract.cpp
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frontend/maxwell/translate/impl/bitfield_insert.cpp
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@ -0,0 +1,35 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/opcodes.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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enum class BitSize : u64 {
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B32,
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B64,
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B96,
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B128,
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};
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void TranslatorVisitor::AL2P(u64 inst) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> result_register;
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BitField<8, 8, IR::Reg> indexing_register;
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BitField<20, 11, s64> offset;
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BitField<47, 2, BitSize> bitsize;
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} al2p{inst};
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if (al2p.bitsize != BitSize::B32) {
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throw NotImplementedException("BitSize {}", al2p.bitsize.Value());
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}
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const IR::U32 converted_offset{ir.Imm32(static_cast<u32>(al2p.offset.Value()))};
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const IR::U32 result{ir.IAdd(X(al2p.indexing_register), converted_offset)};
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X(al2p.result_register, result);
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}
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} // namespace Shader::Maxwell
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@ -13,10 +13,6 @@ namespace Shader::Maxwell {
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throw NotImplementedException("Instruction {} is not implemented", opcode);
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}
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void TranslatorVisitor::AL2P(u64) {
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ThrowNotImplemented(Opcode::AL2P);
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}
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void TranslatorVisitor::ATOM_cas(u64) {
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ThrowNotImplemented(Opcode::ATOM_cas);
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}
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