mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-08-23 01:30:41 +02:00
commit
11bd6024fb
@ -51,13 +51,18 @@ enum {
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EXCLUSIVE_STATE,
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EXCLUSIVE_RESULT,
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// VFP registers
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VFP_BASE,
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VFP_FPSID = VFP_BASE,
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MAX_REG_NUM,
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};
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// VFP system registers
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enum {
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VFP_FPSID,
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VFP_FPSCR,
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VFP_FPEXC,
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MAX_REG_NUM,
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// Not an actual register.
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// All VFP system registers should be defined above this.
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VFP_SYSTEM_REGISTER_COUNT
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};
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enum CP15Register {
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@ -176,5 +181,3 @@ enum CP15Register {
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// All registers should be defined above this.
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CP15_REGISTER_COUNT,
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};
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#define VFP_OFFSET(x) (x - VFP_BASE)
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@ -92,13 +92,15 @@ struct ARMul_State
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ARMword exclusive_state;
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ARMword exclusive_result;
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ARMword CP15[CP15_REGISTER_COUNT];
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ARMword VFP[3]; // FPSID, FPSCR, and FPEXC
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// FPSID, FPSCR, and FPEXC
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ARMword VFP[VFP_SYSTEM_REGISTER_COUNT];
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// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
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// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
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// and only 32 singleword registers are accessible (S0-S31).
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ARMword ExtReg[VFP_REG_NUM];
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/* ---- End of the ordered registers ---- */
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ARMword RegBank[7][16]; // all the registers
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ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
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@ -7,15 +7,15 @@
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#pragma once
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// FPSID Information
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// ARM11 MPCore FPSID Information
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// Note that these are used as values and not as flags.
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enum : u32 {
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VFP_FPSID_IMPLMEN = 0, // Implementation code. Should be the same as cp15 0 c0 0
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VFP_FPSID_SW = 0, // Software emulation bit value
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VFP_FPSID_SUBARCH = 0x2, // Subarchitecture version number
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VFP_FPSID_PARTNUM = 0x1, // Part number
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VFP_FPSID_VARIANT = 0x1, // Variant number
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VFP_FPSID_REVISION = 0x1 // Revision number
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VFP_FPSID_IMPLMEN = 0x41, // Implementation code. Should be the same as cp15 0 c0 0
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VFP_FPSID_SW = 0, // Software emulation bit value
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VFP_FPSID_SUBARCH = 0x1, // Subarchitecture version number
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VFP_FPSID_PARTNUM = 0x20, // Part number
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VFP_FPSID_VARIANT = 0xB, // Variant number
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VFP_FPSID_REVISION = 0x4 // Revision number
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};
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// FPEXC bits
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@ -29,10 +29,10 @@
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unsigned VFPInit(ARMul_State* state)
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{
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state->VFP[VFP_OFFSET(VFP_FPSID)] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 |
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VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION;
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state->VFP[VFP_OFFSET(VFP_FPEXC)] = 0;
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state->VFP[VFP_OFFSET(VFP_FPSCR)] = 0;
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state->VFP[VFP_FPSID] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 |
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VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION;
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state->VFP[VFP_FPEXC] = 0;
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state->VFP[VFP_FPSCR] = 0;
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return 0;
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}
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@ -314,11 +314,11 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
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int exceptions = 0;
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if (CoProc == 10)
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exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
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exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_FPSCR]);
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else
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exceptions = vfp_double_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
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exceptions = vfp_double_cpdo(state, instr, state->VFP[VFP_FPSCR]);
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vfp_raise_exceptions(state, exceptions, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
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vfp_raise_exceptions(state, exceptions, instr, state->VFP[VFP_FPSCR]);
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return ARMul_DONE;
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}
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@ -344,11 +344,11 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
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{
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if (Rt != 15)
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{
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*value = state->VFP[VFP_OFFSET(VFP_FPSCR)];
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*value = state->VFP[VFP_FPSCR];
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}
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else
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{
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*value = state->VFP[VFP_OFFSET(VFP_FPSCR)] ;
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*value = state->VFP[VFP_FPSCR] ;
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}
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}
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else
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@ -356,7 +356,7 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
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switch (reg)
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{
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case 0:
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*value = state->VFP[VFP_OFFSET(VFP_FPSID)];
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*value = state->VFP[VFP_FPSID];
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break;
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case 6:
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/* MVFR1, VFPv3 only ? */
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@ -367,7 +367,7 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
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LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt);
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break;
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case 8:
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*value = state->VFP[VFP_OFFSET(VFP_FPEXC)];
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*value = state->VFP[VFP_FPEXC];
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break;
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default:
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LOG_TRACE(Core_ARM11, "\tSUBARCHITECTURE DEFINED\n");
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@ -407,11 +407,11 @@ void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
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{
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if (reg == 1)
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{
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state->VFP[VFP_OFFSET(VFP_FPSCR)] = state->Reg[Rt];
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state->VFP[VFP_FPSCR] = state->Reg[Rt];
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}
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else if (reg == 8)
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{
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state->VFP[VFP_OFFSET(VFP_FPEXC)] = state->Reg[Rt];
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state->VFP[VFP_FPEXC] = state->Reg[Rt];
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}
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}
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@ -774,5 +774,5 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
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fpscr |= exceptions;
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state->VFP[VFP_OFFSET(VFP_FPSCR)] = fpscr;
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state->VFP[VFP_FPSCR] = fpscr;
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}
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@ -25,7 +25,7 @@
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#define VFP_DEBUG_UNIMPLEMENTED(x) LOG_ERROR(Core_ARM11, "in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1);
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#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested\n", __FUNCTION__);
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#define CHECK_VFP_ENABLED
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#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);}
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#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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unsigned VFPInit(ARMul_State* state);
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unsigned VFPMRC(ARMul_State* state, unsigned type, ARMword instr, ARMword* value);
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@ -46,9 +46,9 @@ VMLA_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -96,9 +96,9 @@ VMLS_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -146,9 +146,9 @@ VNMLA_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -197,9 +197,9 @@ VNMLS_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -247,9 +247,9 @@ VNMUL_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -297,9 +297,9 @@ VMUL_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -347,9 +347,9 @@ VADD_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -397,9 +397,9 @@ VSUB_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -447,9 +447,9 @@ VDIV_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -591,9 +591,9 @@ VABS_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -642,9 +642,9 @@ VNEG_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -692,9 +692,9 @@ VSQRT_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -742,9 +742,9 @@ VCMP_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -792,9 +792,9 @@ VCMP2_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -842,9 +842,9 @@ VCVTBDS_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -894,9 +894,9 @@ VCVTBFF_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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CHECK_VFP_CDP_RET;
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}
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@ -944,9 +944,9 @@ VCVTBFI_INST:
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int ret;
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if (inst_cream->dp_operation)
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
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ret = vfp_double_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
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else
|
||||
ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
|
||||
ret = vfp_single_cpdo(cpu, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
|
||||
|
||||
CHECK_VFP_CDP_RET;
|
||||
}
|
||||
@ -1146,14 +1146,14 @@ VMRS_INST:
|
||||
{
|
||||
if (inst_cream->Rt != 15)
|
||||
{
|
||||
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSCR)];
|
||||
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPSCR];
|
||||
}
|
||||
else
|
||||
{
|
||||
cpu->NFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 31) & 1;
|
||||
cpu->ZFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 30) & 1;
|
||||
cpu->CFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 29) & 1;
|
||||
cpu->VFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 28) & 1;
|
||||
cpu->NFlag = (cpu->VFP[VFP_FPSCR] >> 31) & 1;
|
||||
cpu->ZFlag = (cpu->VFP[VFP_FPSCR] >> 30) & 1;
|
||||
cpu->CFlag = (cpu->VFP[VFP_FPSCR] >> 29) & 1;
|
||||
cpu->VFlag = (cpu->VFP[VFP_FPSCR] >> 28) & 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -1161,7 +1161,7 @@ VMRS_INST:
|
||||
switch (inst_cream->reg)
|
||||
{
|
||||
case 0:
|
||||
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSID)];
|
||||
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPSID];
|
||||
break;
|
||||
case 6:
|
||||
/* MVFR1, VFPv3 only ? */
|
||||
@ -1172,7 +1172,7 @@ VMRS_INST:
|
||||
LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", inst_cream->Rt);
|
||||
break;
|
||||
case 8:
|
||||
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPEXC)];
|
||||
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPEXC];
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
Loading…
Reference in New Issue
Block a user