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Shader_Ir: Implement F16 Variants of F2F, F2I, I2F.
This commit takes care of implementing the F16 Variants of the conversion instructions and makes sure conversions are done.
This commit is contained in:
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0a67416971
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@ -1018,8 +1018,6 @@ union Instruction {
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} f2i;
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union {
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BitField<8, 2, Register::Size> src_size;
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BitField<10, 2, Register::Size> dst_size;
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BitField<39, 4, u64> rounding;
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// H0, H1 extract for F16 missing
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BitField<41, 1, u64> selector; // Guessed as some games set it, TODO: reverse this value
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@ -1122,6 +1122,16 @@ private:
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Type::Float);
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}
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std::string FCastHalf0(Operation operation) {
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const std::string op_a = VisitOperand(operation, 0, Type::HalfFloat);
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return fmt::format("({})[0]", op_a);
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}
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std::string FCastHalf1(Operation operation) {
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const std::string op_a = VisitOperand(operation, 0, Type::HalfFloat);
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return fmt::format("({})[1]", op_a);
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}
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template <Type type>
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std::string Min(Operation operation) {
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return GenerateBinaryCall(operation, "min", type, type, type);
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@ -1278,6 +1288,11 @@ private:
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return ApplyPrecise(operation, BitwiseCastResult(clamped, Type::HalfFloat));
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}
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std::string HCastFloat(Operation operation) {
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const std::string op_a = VisitOperand(operation, 0, Type::Float);
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return fmt::format("fromHalf2(vec2({}, 0.0f))", op_a);
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}
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std::string HUnpack(Operation operation) {
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const std::string operand{VisitOperand(operation, 0, Type::HalfFloat)};
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const auto value = [&]() -> std::string {
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@ -1718,6 +1733,8 @@ private:
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&GLSLDecompiler::Negate<Type::Float>,
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&GLSLDecompiler::Absolute<Type::Float>,
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&GLSLDecompiler::FClamp,
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&GLSLDecompiler::FCastHalf0,
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&GLSLDecompiler::FCastHalf1,
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&GLSLDecompiler::Min<Type::Float>,
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&GLSLDecompiler::Max<Type::Float>,
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&GLSLDecompiler::FCos,
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@ -1778,6 +1795,7 @@ private:
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&GLSLDecompiler::Absolute<Type::HalfFloat>,
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&GLSLDecompiler::HNegate,
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&GLSLDecompiler::HClamp,
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&GLSLDecompiler::HCastFloat,
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&GLSLDecompiler::HUnpack,
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&GLSLDecompiler::HMergeF32,
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&GLSLDecompiler::HMergeH0,
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@ -735,6 +735,16 @@ private:
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return {};
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}
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Id FCastHalf0(Operation operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id FCastHalf1(Operation operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id HNegate(Operation operation) {
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UNIMPLEMENTED();
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return {};
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@ -745,6 +755,11 @@ private:
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return {};
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}
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Id HCastFloat(Operation operation) {
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UNIMPLEMENTED();
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return {};
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}
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Id HUnpack(Operation operation) {
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UNIMPLEMENTED();
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return {};
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@ -1210,6 +1225,8 @@ private:
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&SPIRVDecompiler::Unary<&Module::OpFNegate, Type::Float>,
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&SPIRVDecompiler::Unary<&Module::OpFAbs, Type::Float>,
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&SPIRVDecompiler::Ternary<&Module::OpFClamp, Type::Float>,
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&SPIRVDecompiler::FCastHalf0,
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&SPIRVDecompiler::FCastHalf1,
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&SPIRVDecompiler::Binary<&Module::OpFMin, Type::Float>,
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&SPIRVDecompiler::Binary<&Module::OpFMax, Type::Float>,
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&SPIRVDecompiler::Unary<&Module::OpCos, Type::Float>,
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@ -1270,6 +1287,7 @@ private:
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&SPIRVDecompiler::Unary<&Module::OpFAbs, Type::HalfFloat>,
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&SPIRVDecompiler::HNegate,
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&SPIRVDecompiler::HClamp,
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&SPIRVDecompiler::HCastFloat,
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&SPIRVDecompiler::HUnpack,
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&SPIRVDecompiler::HMergeF32,
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&SPIRVDecompiler::HMergeH0,
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@ -57,7 +57,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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case OpCode::Id::I2F_R:
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case OpCode::Id::I2F_C:
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case OpCode::Id::I2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.selector);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in I2F is not implemented");
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@ -82,14 +82,19 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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value = GetOperandAbsNegFloat(value, false, instr.conversion.negate_a);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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if (instr.conversion.dst_size == Register::Size::Short) {
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value = Operation(OperationCode::HCastFloat, PRECISE, value);
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}
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::F2F_R:
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case OpCode::Id::F2F_C:
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case OpCode::Id::F2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.f2f.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.f2f.src_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in F2F is not implemented");
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@ -107,6 +112,11 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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}
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}();
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if (instr.conversion.src_size == Register::Size::Short) {
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// TODO: figure where extract is sey in the encoding
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value = Operation(OperationCode::FCastHalf0, PRECISE, value);
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}
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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value = [&]() {
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@ -124,19 +134,24 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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default:
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UNIMPLEMENTED_MSG("Unimplemented F2F rounding mode {}",
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static_cast<u32>(instr.conversion.f2f.rounding.Value()));
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return Immediate(0);
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return value;
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}
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}();
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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if (instr.conversion.dst_size == Register::Size::Short) {
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value = Operation(OperationCode::HCastFloat, PRECISE, value);
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}
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::F2I_R:
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case OpCode::Id::F2I_C:
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case OpCode::Id::F2I_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.src_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in F2I is not implemented");
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Node value = [&]() {
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@ -153,6 +168,11 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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}
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}();
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if (instr.conversion.src_size == Register::Size::Short) {
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// TODO: figure where extract is sey in the encoding
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value = Operation(OperationCode::FCastHalf0, PRECISE, value);
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}
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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value = [&]() {
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@ -30,6 +30,8 @@ enum class OperationCode {
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FNegate, /// (MetaArithmetic, float a) -> float
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FAbsolute, /// (MetaArithmetic, float a) -> float
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FClamp, /// (MetaArithmetic, float value, float min, float max) -> float
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FCastHalf0, /// (MetaArithmetic, f16vec2 a) -> float
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FCastHalf1, /// (MetaArithmetic, f16vec2 a) -> float
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FMin, /// (MetaArithmetic, float a, float b) -> float
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FMax, /// (MetaArithmetic, float a, float b) -> float
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FCos, /// (MetaArithmetic, float a) -> float
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@ -83,17 +85,18 @@ enum class OperationCode {
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UBitfieldExtract, /// (MetaArithmetic, uint value, int offset, int offset) -> uint
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UBitCount, /// (MetaArithmetic, uint) -> uint
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HAdd, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HMul, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HFma, /// (MetaArithmetic, f16vec2 a, f16vec2 b, f16vec2 c) -> f16vec2
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HAbsolute, /// (f16vec2 a) -> f16vec2
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HNegate, /// (f16vec2 a, bool first, bool second) -> f16vec2
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HClamp, /// (f16vec2 src, float min, float max) -> f16vec2
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HUnpack, /// (Tegra::Shader::HalfType, T value) -> f16vec2
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HMergeF32, /// (f16vec2 src) -> float
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HMergeH0, /// (f16vec2 dest, f16vec2 src) -> f16vec2
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HMergeH1, /// (f16vec2 dest, f16vec2 src) -> f16vec2
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HPack2, /// (float a, float b) -> f16vec2
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HAdd, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HMul, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HFma, /// (MetaArithmetic, f16vec2 a, f16vec2 b, f16vec2 c) -> f16vec2
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HAbsolute, /// (f16vec2 a) -> f16vec2
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HNegate, /// (f16vec2 a, bool first, bool second) -> f16vec2
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HClamp, /// (f16vec2 src, float min, float max) -> f16vec2
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HCastFloat, /// (MetaArithmetic, float a) -> f16vec2
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HUnpack, /// (Tegra::Shader::HalfType, T value) -> f16vec2
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HMergeF32, /// (f16vec2 src) -> float
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HMergeH0, /// (f16vec2 dest, f16vec2 src) -> f16vec2
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HMergeH1, /// (f16vec2 dest, f16vec2 src) -> f16vec2
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HPack2, /// (float a, float b) -> f16vec2
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LogicalAssign, /// (bool& dst, bool src) -> void
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LogicalAnd, /// (bool a, bool b) -> bool
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