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https://github.com/yuzu-emu/yuzu.git
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Merge pull request #774 from lioncash/decodings
dyncom: Add ARMv6K NOP and hint instructions to the interpreter.
This commit is contained in:
commit
12f6216741
@ -181,7 +181,11 @@ const ISEITEM arm_instruction[] = {
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{ "ldrt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003 },
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{ "mrc", 3, 6, 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001 },
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{ "mcr", 3, 0, 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001 },
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{ "msr", 2, 0, 23, 27, 0x00000006, 20, 21, 0x00000002 },
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{ "msr", 3, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000001 },
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{ "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 19, 0x00000004 },
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{ "msr", 5, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 19, 19, 0x00000001, 16, 17, 0x00000000 },
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{ "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 17, 0x00000001 },
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{ "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 17, 17, 0x00000001 },
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{ "ldrb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001 },
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{ "strb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000 },
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{ "ldr", 4, 0, 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 },
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@ -190,12 +194,17 @@ const ISEITEM arm_instruction[] = {
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{ "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 },
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{ "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 },
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{ "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 },
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{ "swi", 1, 0, 24, 27, 0x0000000f },
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{ "bbl", 1, 0, 25, 27, 0x00000005 },
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{ "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 },
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{ "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 },
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{ "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 },
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{ "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 },
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{ "nop", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000000 },
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{ "yield", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000001 },
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{ "wfe", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000002 },
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{ "wfi", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000003 },
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{ "sev", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000004 },
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{ "swi", 1, 0, 24, 27, 0x0000000f },
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{ "bbl", 1, 0, 25, 27, 0x00000005 },
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};
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const ISEITEM arm_exclusion_code[] = {
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@ -375,6 +384,10 @@ const ISEITEM arm_exclusion_code[] = {
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{ "mrc", 0, 6, 0 },
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{ "mcr", 0, 0, 0 },
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{ "msr", 0, 0, 0 },
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{ "msr", 0, 0, 0 },
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{ "msr", 0, 0, 0 },
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{ "msr", 0, 0, 0 },
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{ "msr", 0, 0, 0 },
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{ "ldrb", 0, 0, 0 },
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{ "strb", 0, 0, 0 },
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{ "ldr", 0, 0, 0 },
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@ -383,12 +396,17 @@ const ISEITEM arm_exclusion_code[] = {
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{ "cdp", 0, 0, 0 },
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{ "stc", 0, 0, 0 },
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{ "ldc", 0, 0, 0 },
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{ "swi", 0, 0, 0 },
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{ "bbl", 0, 0, 0 },
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{ "ldrexd", 0, ARMV6K, 0 },
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{ "strexd", 0, ARMV6K, 0 },
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{ "ldrexh", 0, ARMV6K, 0 },
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{ "strexh", 0, ARMV6K, 0 },
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{ "nop", 0, ARMV6K, 0 },
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{ "yield", 0, ARMV6K, 0 },
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{ "wfe", 0, ARMV6K, 0 },
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{ "wfi", 0, ARMV6K, 0 },
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{ "sev", 0, ARMV6K, 0 },
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{ "swi", 0, 0, 0 },
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{ "bbl", 0, 0, 0 },
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{ "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4]
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{ "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3]
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@ -2037,6 +2037,19 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index)
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return inst_base;
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}
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// NOP introduced in ARMv6K.
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static ARM_INST_PTR INTERPRETER_TRANSLATE(nop)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst));
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@ -2328,6 +2341,18 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index)
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(sev)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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@ -3332,6 +3357,40 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index)
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return INTERPRETER_TRANSLATE(uxtab16)(inst, index);
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(wfe)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(wfi)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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return inst_base;
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}
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static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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return inst_base;
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}
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// Floating point VFPv3 structures and instructions
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#define VFP_INTERPRETER_STRUCT
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@ -3521,6 +3580,10 @@ const transop_fp_t arm_instruction_trans[] = {
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INTERPRETER_TRANSLATE(mrc),
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INTERPRETER_TRANSLATE(mcr),
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INTERPRETER_TRANSLATE(msr),
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INTERPRETER_TRANSLATE(msr),
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INTERPRETER_TRANSLATE(msr),
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INTERPRETER_TRANSLATE(msr),
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INTERPRETER_TRANSLATE(msr),
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INTERPRETER_TRANSLATE(ldrb),
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INTERPRETER_TRANSLATE(strb),
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INTERPRETER_TRANSLATE(ldr),
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@ -3529,12 +3592,17 @@ const transop_fp_t arm_instruction_trans[] = {
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INTERPRETER_TRANSLATE(cdp),
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INTERPRETER_TRANSLATE(stc),
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INTERPRETER_TRANSLATE(ldc),
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INTERPRETER_TRANSLATE(swi),
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INTERPRETER_TRANSLATE(bbl),
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INTERPRETER_TRANSLATE(ldrexd),
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INTERPRETER_TRANSLATE(strexd),
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INTERPRETER_TRANSLATE(ldrexh),
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INTERPRETER_TRANSLATE(strexh),
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INTERPRETER_TRANSLATE(nop),
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INTERPRETER_TRANSLATE(yield),
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INTERPRETER_TRANSLATE(wfe),
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INTERPRETER_TRANSLATE(wfi),
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INTERPRETER_TRANSLATE(sev),
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INTERPRETER_TRANSLATE(swi),
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INTERPRETER_TRANSLATE(bbl),
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// All the thumb instructions should be placed the end of table
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INTERPRETER_TRANSLATE(b_2_thumb),
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@ -3709,6 +3777,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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inst_base = (arm_inst *)&inst_buf[ptr]
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#define INC_PC(l) ptr += sizeof(arm_inst) + l
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#define INC_PC_STUB ptr += sizeof(arm_inst)
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// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a
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// clunky switch statement.
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@ -3897,28 +3966,37 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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case 172: goto MRC_INST; \
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case 173: goto MCR_INST; \
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case 174: goto MSR_INST; \
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case 175: goto LDRB_INST; \
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case 176: goto STRB_INST; \
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case 177: goto LDR_INST; \
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case 178: goto LDRCOND_INST ; \
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case 179: goto STR_INST; \
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case 180: goto CDP_INST; \
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case 181: goto STC_INST; \
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case 182: goto LDC_INST; \
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case 183: goto SWI_INST; \
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case 184: goto BBL_INST; \
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case 185: goto LDREXD_INST; \
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case 186: goto STREXD_INST; \
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case 187: goto LDREXH_INST; \
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case 188: goto STREXH_INST; \
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case 189: goto B_2_THUMB ; \
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case 190: goto B_COND_THUMB ; \
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case 191: goto BL_1_THUMB ; \
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case 192: goto BL_2_THUMB ; \
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case 193: goto BLX_1_THUMB ; \
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case 194: goto DISPATCH; \
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case 195: goto INIT_INST_LENGTH; \
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case 196: goto END; \
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case 175: goto MSR_INST; \
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case 176: goto MSR_INST; \
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case 177: goto MSR_INST; \
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case 178: goto MSR_INST; \
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case 179: goto LDRB_INST; \
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case 180: goto STRB_INST; \
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case 181: goto LDR_INST; \
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case 182: goto LDRCOND_INST ; \
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case 183: goto STR_INST; \
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case 184: goto CDP_INST; \
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case 185: goto STC_INST; \
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case 186: goto LDC_INST; \
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case 187: goto LDREXD_INST; \
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case 188: goto STREXD_INST; \
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case 189: goto LDREXH_INST; \
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case 190: goto STREXH_INST; \
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case 191: goto NOP_INST; \
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case 192: goto YIELD_INST; \
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case 193: goto WFE_INST; \
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case 194: goto WFI_INST; \
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case 195: goto SEV_INST; \
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case 196: goto SWI_INST; \
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case 197: goto BBL_INST; \
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case 198: goto B_2_THUMB ; \
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case 199: goto B_COND_THUMB ; \
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case 200: goto BL_1_THUMB ; \
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case 201: goto BL_2_THUMB ; \
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case 202: goto BLX_1_THUMB ; \
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case 203: goto DISPATCH; \
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case 204: goto INIT_INST_LENGTH; \
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case 205: goto END; \
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}
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#endif
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@ -3964,9 +4042,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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&&MCRR_INST,&&MRRC_INST,&&CMP_INST,&&TST_INST,&&TEQ_INST,&&CMN_INST,&&SMULL_INST,&&UMULL_INST,&&UMLAL_INST,&&SMLAL_INST,&&MUL_INST,
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&&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST,
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&&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST,
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&&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST,
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&&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST,
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&&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
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&&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,
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&&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST,
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&&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST,
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&&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&NOP_INST, &&YIELD_INST, &&WFE_INST, &&WFI_INST, &&SEV_INST, &&SWI_INST,&&BBL_INST,
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&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH,
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&&INIT_INST_LENGTH,&&END
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};
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#endif
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@ -5019,6 +5099,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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GOTO_NEXT_INST;
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}
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NOP_INST:
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{
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC_STUB;
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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PKHBT_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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@ -5502,6 +5590,19 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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GOTO_NEXT_INST;
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}
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SEV_INST:
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{
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// Stubbed, as SEV is a hint instruction.
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "SEV executed.");
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC_STUB;
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SHADD8_INST:
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SHADD16_INST:
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SHADDSUBX_INST:
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@ -6965,6 +7066,45 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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GOTO_NEXT_INST;
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}
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WFE_INST:
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{
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// Stubbed, as WFE is a hint instruction.
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "WFE executed.");
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC_STUB;
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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WFI_INST:
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{
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// Stubbed, as WFI is a hint instruction.
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "WFI executed.");
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC_STUB;
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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YIELD_INST:
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{
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// Stubbed, as YIELD is a hint instruction.
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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LOG_TRACE(Core_ARM11, "YIELD executed.");
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC_STUB;
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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#define VFP_INTERPRETER_IMPL
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_INTERPRETER_IMPL
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