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https://github.com/yuzu-emu/yuzu.git
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commit
1ccc0457d5
@ -332,6 +332,10 @@ union Instruction {
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} ipa;
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union {
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BitField<39, 2, u64> tab5cb8_2;
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BitField<41, 3, u64> tab5c68_1;
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BitField<44, 2, u64> tab5c68_0;
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BitField<47, 1, u64> cc;
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BitField<48, 1, u64> negate_b;
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} fmul;
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@ -1038,6 +1038,15 @@ private:
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
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ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented",
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instr.fmul.tab5cb8_2.Value());
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ASSERT_MSG(instr.fmul.tab5c68_1 == 0, "FMUL tab5cb8_1({}) is not implemented",
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instr.fmul.tab5c68_1.Value());
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ASSERT_MSG(instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented",
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instr.fmul.tab5c68_0
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.Value()); // SMO typical sends 1 here which seems to be the default
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ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented");
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op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,
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instr.alu.saturate_d);
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