mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-08-21 15:13:23 +02:00
video_core/shader: Resolve instances of variable shadowing
Silences a few -Wshadow warnings.
This commit is contained in:
parent
012d7f5233
commit
1f5401c89c
@ -144,7 +144,7 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
|
||||
case OpCode::Id::ICMP_IMM: {
|
||||
const Node zero = Immediate(0);
|
||||
|
||||
const auto [op_b, test] = [&]() -> std::pair<Node, Node> {
|
||||
const auto [op_rhs, test] = [&]() -> std::pair<Node, Node> {
|
||||
switch (opcode->get().GetId()) {
|
||||
case OpCode::Id::ICMP_CR:
|
||||
return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
|
||||
@ -161,10 +161,10 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
|
||||
return {zero, zero};
|
||||
}
|
||||
}();
|
||||
const Node op_a = GetRegister(instr.gpr8);
|
||||
const Node op_lhs = GetRegister(instr.gpr8);
|
||||
const Node comparison =
|
||||
GetPredicateComparisonInteger(instr.icmp.cond, instr.icmp.is_signed != 0, test, zero);
|
||||
SetRegister(bb, instr.gpr0, Operation(OperationCode::Select, comparison, op_a, op_b));
|
||||
SetRegister(bb, instr.gpr0, Operation(OperationCode::Select, comparison, op_lhs, op_rhs));
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::LOP_C:
|
||||
|
@ -144,8 +144,8 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
|
||||
|
||||
Image& ShaderIR::GetImage(Tegra::Shader::Image image, Tegra::Shader::ImageType type) {
|
||||
const auto offset{static_cast<std::size_t>(image.index.Value())};
|
||||
if (const auto image = TryUseExistingImage(offset, type)) {
|
||||
return *image;
|
||||
if (const auto existing_image = TryUseExistingImage(offset, type)) {
|
||||
return *existing_image;
|
||||
}
|
||||
|
||||
const std::size_t next_index{used_images.size()};
|
||||
|
@ -67,7 +67,7 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::MOV_SYS: {
|
||||
const Node value = [&]() {
|
||||
const Node value = [this, instr] {
|
||||
switch (instr.sys20) {
|
||||
case SystemVariable::Ydirection:
|
||||
return Operation(OperationCode::YNegate);
|
||||
|
@ -18,7 +18,7 @@ u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
|
||||
const auto opcode = OpCode::Decode(instr);
|
||||
|
||||
Node op_a = GetRegister(instr.gpr8);
|
||||
Node op_b = [&]() {
|
||||
Node op_b = [this, instr] {
|
||||
if (instr.is_b_imm) {
|
||||
return Immediate(instr.alu.GetSignedImm20_20());
|
||||
} else if (instr.is_b_gpr) {
|
||||
|
@ -23,7 +23,7 @@ u32 ShaderIR::DecodeVideo(NodeBlock& bb, u32 pc) {
|
||||
const Node op_a =
|
||||
GetVideoOperand(GetRegister(instr.gpr8), instr.video.is_byte_chunk_a, instr.video.signed_a,
|
||||
instr.video.type_a, instr.video.byte_height_a);
|
||||
const Node op_b = [&]() {
|
||||
const Node op_b = [this, instr] {
|
||||
if (instr.video.use_register_b) {
|
||||
return GetVideoOperand(GetRegister(instr.gpr20), instr.video.is_byte_chunk_b,
|
||||
instr.video.signed_b, instr.video.type_b,
|
||||
|
@ -46,9 +46,10 @@ u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) {
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::SHFL: {
|
||||
Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm))
|
||||
: GetRegister(instr.gpr39);
|
||||
Node width = [&] {
|
||||
Node width = [this, instr] {
|
||||
Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm))
|
||||
: GetRegister(instr.gpr39);
|
||||
|
||||
// Convert the obscure SHFL mask back into GL_NV_shader_thread_shuffle's width. This has
|
||||
// been done reversing Nvidia's math. It won't work on all cases due to SHFL having
|
||||
// different parameters that don't properly map to GLSL's interface, but it should work
|
||||
|
Loading…
Reference in New Issue
Block a user