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shader: Implement IMNMX
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08a9e95905
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20390c0548
@ -71,6 +71,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/impl.cpp
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frontend/maxwell/translate/impl/impl.h
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frontend/maxwell/translate/impl/integer_add.cpp
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frontend/maxwell/translate/impl/integer_minimum_maximum.cpp
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frontend/maxwell/translate/impl/integer_popcount.cpp
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frontend/maxwell/translate/impl/integer_scaled_add.cpp
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frontend/maxwell/translate/impl/integer_set_predicate.cpp
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@ -230,6 +230,10 @@ Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitReverse32(EmitContext& ctx, Id value);
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Id EmitBitCount32(EmitContext& ctx, Id value);
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Id EmitBitwiseNot32(EmitContext& ctx, Id a);
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Id EmitSMin32(EmitContext& ctx, Id a, Id b);
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Id EmitUMin32(EmitContext& ctx, Id a, Id b);
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Id EmitSMax32(EmitContext& ctx, Id a, Id b);
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Id EmitUMax32(EmitContext& ctx, Id a, Id b);
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
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Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
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@ -114,6 +114,22 @@ Id EmitBitwiseNot32(EmitContext& ctx, Id a) {
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return ctx.OpNot(ctx.U32[1], a);
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}
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Id EmitSMin32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSMin(ctx.U32[1], a, b);
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}
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Id EmitUMin32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUMin(ctx.U32[1], a, b);
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}
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Id EmitSMax32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSMax(ctx.U32[1], a, b);
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}
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Id EmitUMax32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUMax(ctx.U32[1], a, b);
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}
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
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return ctx.OpSLessThan(ctx.U1, lhs, rhs);
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}
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@ -816,6 +816,22 @@ U32 IREmitter::BitwiseNot(const U32& a) {
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return Inst<U32>(Opcode::BitwiseNot32, a);
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}
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U32 IREmitter::SMin(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::SMin32, a, b);
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}
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U32 IREmitter::UMin(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::UMin32, a, b);
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}
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U32 IREmitter::SMax(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::SMax32, a, b);
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}
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U32 IREmitter::UMax(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::UMax32, a, b);
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}
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U1 IREmitter::ILessThan(const U32& lhs, const U32& rhs, bool is_signed) {
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return Inst<U1>(is_signed ? Opcode::SLessThan : Opcode::ULessThan, lhs, rhs);
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}
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@ -163,6 +163,11 @@ public:
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[[nodiscard]] U32 BitCount(const U32& value);
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[[nodiscard]] U32 BitwiseNot(const U32& a);
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[[nodiscard]] U32 SMin(const U32& a, const U32& b);
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[[nodiscard]] U32 UMin(const U32& a, const U32& b);
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[[nodiscard]] U32 SMax(const U32& a, const U32& b);
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[[nodiscard]] U32 UMax(const U32& a, const U32& b);
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[[nodiscard]] U1 ILessThan(const U32& lhs, const U32& rhs, bool is_signed);
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[[nodiscard]] U1 IEqual(const U32& lhs, const U32& rhs);
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[[nodiscard]] U1 ILessThanEqual(const U32& lhs, const U32& rhs, bool is_signed);
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@ -235,6 +235,10 @@ OPCODE(BitReverse32, U32, U32,
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OPCODE(BitCount32, U32, U32, )
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OPCODE(BitwiseNot32, U32, U32, )
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OPCODE(SMin32, U32, U32, U32, )
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OPCODE(UMin32, U32, U32, U32, )
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OPCODE(SMax32, U32, U32, U32, )
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OPCODE(UMax32, U32, U32, U32, )
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OPCODE(SLessThan, U1, U32, U32, )
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OPCODE(ULessThan, U1, U32, U32, )
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OPCODE(IEqual, U1, U32, U32, )
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@ -0,0 +1,59 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void IMNMX(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<39, 3, IR::Pred> pred;
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BitField<42, 1, u64> neg_pred;
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BitField<43, 2, u64> mode;
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BitField<48, 1, u64> is_signed;
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} const imnmx{insn};
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if (imnmx.mode != 0) {
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throw NotImplementedException("IMNMX.MODE");
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}
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IR::U1 pred = v.ir.GetPred(imnmx.pred);
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const IR::U32 op_a{v.X(imnmx.src_reg)};
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IR::U32 min;
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IR::U32 max;
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if (imnmx.is_signed != 0) {
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min = IR::U32{v.ir.SMin(op_a, op_b)};
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max = IR::U32{v.ir.SMax(op_a, op_b)};
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} else {
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min = IR::U32{v.ir.UMin(op_a, op_b)};
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max = IR::U32{v.ir.UMax(op_a, op_b)};
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}
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if (imnmx.neg_pred != 0) {
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std::swap(min, max);
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}
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const IR::U32 result{v.ir.Select(pred, min, max)};
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v.X(imnmx.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::IMNMX_reg(u64 insn) {
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IMNMX(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::IMNMX_cbuf(u64 insn) {
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IMNMX(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::IMNMX_imm(u64 insn) {
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IMNMX(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -453,18 +453,6 @@ void TranslatorVisitor::IMADSP_imm(u64) {
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ThrowNotImplemented(Opcode::IMADSP_imm);
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}
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void TranslatorVisitor::IMNMX_reg(u64) {
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ThrowNotImplemented(Opcode::IMNMX_reg);
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}
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void TranslatorVisitor::IMNMX_cbuf(u64) {
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ThrowNotImplemented(Opcode::IMNMX_cbuf);
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}
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void TranslatorVisitor::IMNMX_imm(u64) {
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ThrowNotImplemented(Opcode::IMNMX_imm);
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}
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void TranslatorVisitor::IMUL_reg(u64) {
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ThrowNotImplemented(Opcode::IMUL_reg);
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}
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