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Merge pull request #193 from N00byKing/3184_2_robotic_boogaloo
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
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commit
23a0d2d7b7
@ -25,19 +25,11 @@ public:
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VAddr tls_address;
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};
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/**
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* Runs the CPU for the given number of instructions
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* @param num_instructions Number of instructions to run
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*/
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void Run(int num_instructions) {
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ExecuteInstructions(num_instructions);
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this->num_instructions += num_instructions;
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}
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/// Runs the CPU until an event happens
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virtual void Run() = 0;
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/// Step CPU by one instruction
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void Step() {
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Run(1);
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}
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virtual void Step() = 0;
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/// Maps a backing memory region for the CPU
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virtual void MapBackingMemory(VAddr address, size_t size, u8* memory,
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@ -126,19 +118,4 @@ public:
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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virtual void PrepareReschedule() = 0;
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/// Getter for num_instructions
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u64 GetNumInstructions() const {
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return num_instructions;
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}
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protected:
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/**
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* Executes the given number of instructions
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* @param num_instructions Number of instructions to executes
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*/
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virtual void ExecuteInstructions(int num_instructions) = 0;
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private:
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u64 num_instructions = 0; ///< Number of instructions executed
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};
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@ -122,11 +122,22 @@ std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_C
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return std::make_unique<Dynarmic::A64::Jit>(config);
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}
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void ARM_Dynarmic::Run() {
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ASSERT(Memory::GetCurrentPageTable() == current_page_table);
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jit->Run();
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}
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void ARM_Dynarmic::Step() {
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cb->InterpreterFallback(jit->GetPC(), 1);
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}
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ARM_Dynarmic::ARM_Dynarmic()
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: cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)), jit(MakeJit(cb)) {
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ARM_Interface::ThreadContext ctx;
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inner_unicorn.SaveContext(ctx);
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LoadContext(ctx);
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PageTableChanged();
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}
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ARM_Dynarmic::~ARM_Dynarmic() = default;
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@ -189,13 +200,6 @@ void ARM_Dynarmic::SetTlsAddress(u64 address) {
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cb->tpidrro_el0 = address;
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}
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void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
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cb->ticks_remaining = num_instructions;
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jit->Run();
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CoreTiming::AddTicks(num_instructions - cb->num_interpreted_instructions);
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cb->num_interpreted_instructions = 0;
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}
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void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
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ctx.cpu_registers = jit->GetRegisters();
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ctx.sp = jit->GetSP();
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@ -228,4 +232,5 @@ void ARM_Dynarmic::ClearInstructionCache() {
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void ARM_Dynarmic::PageTableChanged() {
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jit = MakeJit(cb);
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current_page_table = Memory::GetCurrentPageTable();
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}
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@ -29,6 +29,8 @@ public:
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u32 GetVFPReg(int index) const override;
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void SetVFPReg(int index, u32 value) override;
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u32 GetCPSR() const override;
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void Run() override;
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void Step() override;
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void SetCPSR(u32 cpsr) override;
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VAddr GetTlsAddress() const override;
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void SetTlsAddress(VAddr address) override;
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@ -37,7 +39,6 @@ public:
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void LoadContext(const ThreadContext& ctx) override;
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void PrepareReschedule() override;
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void ExecuteInstructions(int num_instructions) override;
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void ClearInstructionCache() override;
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void PageTableChanged() override;
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@ -47,4 +48,6 @@ private:
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std::unique_ptr<ARM_Dynarmic_Callbacks> cb;
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std::unique_ptr<Dynarmic::A64::Jit> jit;
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ARM_Unicorn inner_unicorn;
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Memory::PageTable* current_page_table = nullptr;
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};
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@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <unicorn/arm64.h>
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#include "common/assert.h"
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#include "common/microprofile.h"
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@ -153,6 +154,14 @@ void ARM_Unicorn::SetTlsAddress(VAddr base) {
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_TPIDRRO_EL0, &base));
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}
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void ARM_Unicorn::Run() {
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ExecuteInstructions(std::max(CoreTiming::GetDowncount(), 0));
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}
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void ARM_Unicorn::Step() {
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ExecuteInstructions(1);
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}
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MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
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void ARM_Unicorn::ExecuteInstructions(int num_instructions) {
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@ -30,7 +30,9 @@ public:
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void SaveContext(ThreadContext& ctx) override;
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void LoadContext(const ThreadContext& ctx) override;
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void PrepareReschedule() override;
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void ExecuteInstructions(int num_instructions) override;
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void ExecuteInstructions(int num_instructions);
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void Run() override;
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void Step() override;
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void ClearInstructionCache() override;
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void PageTableChanged() override{};
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@ -26,7 +26,7 @@ namespace Core {
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/*static*/ System System::s_instance;
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System::ResultStatus System::RunLoop(int tight_loop) {
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System::ResultStatus System::RunLoop(bool tight_loop) {
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status = ResultStatus::Success;
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if (!cpu_core) {
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return ResultStatus::ErrorNotInitialized;
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@ -40,7 +40,7 @@ System::ResultStatus System::RunLoop(int tight_loop) {
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if (GDBStub::GetCpuHaltFlag()) {
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if (GDBStub::GetCpuStepFlag()) {
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GDBStub::SetCpuStepFlag(false);
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tight_loop = 1;
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tight_loop = false;
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} else {
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return ResultStatus::Success;
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}
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@ -56,7 +56,11 @@ System::ResultStatus System::RunLoop(int tight_loop) {
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PrepareReschedule();
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} else {
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CoreTiming::Advance();
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cpu_core->Run(tight_loop);
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if (tight_loop) {
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cpu_core->Run();
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} else {
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cpu_core->Step();
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}
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}
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HW::Update();
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@ -66,7 +70,7 @@ System::ResultStatus System::RunLoop(int tight_loop) {
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}
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System::ResultStatus System::SingleStep() {
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return RunLoop(1);
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return RunLoop(false);
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}
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System::ResultStatus System::Load(EmuWindow* emu_window, const std::string& filepath) {
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@ -53,10 +53,10 @@ public:
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* is not required to do a full dispatch with each instruction. NOTE: the number of instructions
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* requested is not guaranteed to run, as this will be interrupted preemptively if a hardware
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* update is requested (e.g. on a thread switch).
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* @param tight_loop Number of instructions to execute.
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* @param tight_loop If false, the CPU single-steps.
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* @return Result status, indicating whether or not the operation succeeded.
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*/
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ResultStatus RunLoop(int tight_loop = 100000);
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ResultStatus RunLoop(bool tight_loop = true);
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/**
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* Step the CPU one instruction
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