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https://github.com/yuzu-emu/yuzu.git
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Merge pull request #1271 from lioncash/dyncom-misc
dyncom: Miscellaneous minor changes
This commit is contained in:
commit
2589a68c42
@ -14,10 +14,6 @@ namespace Core {
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/// Generic ARM11 CPU interface
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/// Generic ARM11 CPU interface
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class ARM_Interface : NonCopyable {
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class ARM_Interface : NonCopyable {
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public:
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public:
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ARM_Interface() {
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num_instructions = 0;
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}
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virtual ~ARM_Interface() {
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virtual ~ARM_Interface() {
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}
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}
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@ -146,11 +142,11 @@ public:
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virtual void PrepareReschedule() = 0;
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virtual void PrepareReschedule() = 0;
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/// Getter for num_instructions
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/// Getter for num_instructions
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u64 GetNumInstructions() {
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u64 GetNumInstructions() const {
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return num_instructions;
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return num_instructions;
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}
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}
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s64 down_count; ///< A decreasing counter of remaining cycles before the next event, decreased by the cpu run loop
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s64 down_count = 0; ///< A decreasing counter of remaining cycles before the next event, decreased by the cpu run loop
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protected:
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protected:
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@ -162,6 +158,5 @@ protected:
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private:
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private:
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u64 num_instructions; ///< Number of instructions executed
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u64 num_instructions = 0; ///< Number of instructions executed
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};
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};
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@ -51,7 +51,7 @@ enum {
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typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
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typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
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static bool CondPassed(ARMul_State* cpu, unsigned int cond) {
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static bool CondPassed(const ARMul_State* cpu, unsigned int cond) {
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const bool n_flag = cpu->NFlag != 0;
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const bool n_flag = cpu->NFlag != 0;
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const bool z_flag = cpu->ZFlag != 0;
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const bool z_flag = cpu->ZFlag != 0;
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const bool c_flag = cpu->CFlag != 0;
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const bool c_flag = cpu->CFlag != 0;
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@ -30,7 +30,7 @@
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* @return If the PC is being read, then the word-aligned PC value is returned.
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* @return If the PC is being read, then the word-aligned PC value is returned.
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* If the PC is not being read, then the value stored in the register is returned.
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* If the PC is not being read, then the value stored in the register is returned.
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*/
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*/
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static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {
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inline u32 CHECK_READ_REG15_WA(const ARMul_State* cpu, int Rn) {
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return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
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return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
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}
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}
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@ -43,6 +43,6 @@ static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {
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* @return If the PC is being read, then the incremented PC value is returned.
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* @return If the PC is being read, then the incremented PC value is returned.
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* If the PC is not being read, then the values stored in the register is returned.
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* If the PC is not being read, then the values stored in the register is returned.
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*/
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*/
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static inline u32 CHECK_READ_REG15(ARMul_State* cpu, int Rn) {
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inline u32 CHECK_READ_REG15(const ARMul_State* cpu, int Rn) {
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return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
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return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
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}
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}
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@ -38,7 +38,7 @@ enum class ThumbDecodeStatus {
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// Translates a Thumb mode instruction into its ARM equivalent.
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// Translates a Thumb mode instruction into its ARM equivalent.
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ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size);
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ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size);
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static inline u32 GetThumbInstruction(u32 instr, u32 address) {
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inline u32 GetThumbInstruction(u32 instr, u32 address) {
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// Normally you would need to handle instruction endianness,
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// Normally you would need to handle instruction endianness,
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// however, it is fixed to little-endian on the MPCore, so
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// however, it is fixed to little-endian on the MPCore, so
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// there's no need to check for this beforehand.
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// there's no need to check for this beforehand.
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@ -85,7 +85,7 @@ enum : u32 {
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#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
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#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
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static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
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inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
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{
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{
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if (shift) {
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if (shift) {
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if (shift < 32)
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if (shift < 32)
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@ -96,7 +96,7 @@ static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
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return val;
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return val;
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}
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}
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static inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
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inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
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{
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{
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if (shift) {
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if (shift) {
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if (shift < 64)
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if (shift < 64)
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@ -107,7 +107,7 @@ static inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
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return val;
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return val;
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}
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}
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static inline u32 vfp_hi64to32jamming(u64 val)
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inline u32 vfp_hi64to32jamming(u64 val)
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{
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{
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u32 v;
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u32 v;
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u32 highval = val >> 32;
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u32 highval = val >> 32;
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@ -121,7 +121,7 @@ static inline u32 vfp_hi64to32jamming(u64 val)
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return v;
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return v;
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}
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}
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static inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
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inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
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{
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{
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*resl = nl + ml;
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*resl = nl + ml;
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*resh = nh + mh;
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*resh = nh + mh;
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@ -129,7 +129,7 @@ static inline void add128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
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*resh += 1;
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*resh += 1;
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}
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}
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static inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
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inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
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{
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{
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*resl = nl - ml;
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*resl = nl - ml;
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*resh = nh - mh;
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*resh = nh - mh;
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@ -137,7 +137,7 @@ static inline void sub128(u64* resh, u64* resl, u64 nh, u64 nl, u64 mh, u64 ml)
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*resh -= 1;
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*resh -= 1;
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}
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}
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static inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m)
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inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m)
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{
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{
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u32 nh, nl, mh, ml;
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u32 nh, nl, mh, ml;
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u64 rh, rma, rmb, rl;
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u64 rh, rma, rmb, rl;
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@ -164,20 +164,20 @@ static inline void mul64to128(u64* resh, u64* resl, u64 n, u64 m)
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*resh = rh;
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*resh = rh;
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}
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}
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static inline void shift64left(u64* resh, u64* resl, u64 n)
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inline void shift64left(u64* resh, u64* resl, u64 n)
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{
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{
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*resh = n >> 63;
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*resh = n >> 63;
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*resl = n << 1;
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*resl = n << 1;
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}
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}
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static inline u64 vfp_hi64multiply64(u64 n, u64 m)
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inline u64 vfp_hi64multiply64(u64 n, u64 m)
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{
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{
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u64 rh, rl;
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u64 rh, rl;
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mul64to128(&rh, &rl, n, m);
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mul64to128(&rh, &rl, n, m);
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return rh | (rl != 0);
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return rh | (rl != 0);
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}
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}
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static inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
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inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
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{
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{
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u64 mh, ml, remh, reml, termh, terml, z;
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u64 mh, ml, remh, reml, termh, terml, z;
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@ -249,7 +249,7 @@ enum : u32 {
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VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL)
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VFP_SNAN = (VFP_NAN|VFP_NAN_SIGNAL)
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};
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};
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static inline int vfp_single_type(vfp_single* s)
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inline int vfp_single_type(const vfp_single* s)
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{
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{
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int type = VFP_NUMBER;
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int type = VFP_NUMBER;
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if (s->exponent == 255) {
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if (s->exponent == 255) {
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@ -271,7 +271,7 @@ static inline int vfp_single_type(vfp_single* s)
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// Unpack a single-precision float. Note that this returns the magnitude
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// Unpack a single-precision float. Note that this returns the magnitude
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// of the single-precision float mantissa with the 1. if necessary,
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// of the single-precision float mantissa with the 1. if necessary,
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// aligned to bit 30.
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// aligned to bit 30.
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static inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
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inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
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{
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{
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s->sign = vfp_single_packed_sign(val) >> 16,
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s->sign = vfp_single_packed_sign(val) >> 16,
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s->exponent = vfp_single_packed_exponent(val);
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s->exponent = vfp_single_packed_exponent(val);
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@ -293,7 +293,7 @@ static inline void vfp_single_unpack(vfp_single* s, s32 val, u32* fpscr)
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// Re-pack a single-precision float. This assumes that the float is
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// Re-pack a single-precision float. This assumes that the float is
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// already normalised such that the MSB is bit 30, _not_ bit 31.
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// already normalised such that the MSB is bit 30, _not_ bit 31.
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static inline s32 vfp_single_pack(vfp_single* s)
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inline s32 vfp_single_pack(const vfp_single* s)
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{
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{
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u32 val = (s->sign << 16) +
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u32 val = (s->sign << 16) +
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(s->exponent << VFP_SINGLE_MANTISSA_BITS) +
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(s->exponent << VFP_SINGLE_MANTISSA_BITS) +
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@ -335,7 +335,7 @@ struct vfp_double {
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#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
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#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
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#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
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#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
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static inline int vfp_double_type(vfp_double* s)
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inline int vfp_double_type(const vfp_double* s)
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{
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{
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int type = VFP_NUMBER;
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int type = VFP_NUMBER;
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if (s->exponent == 2047) {
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if (s->exponent == 2047) {
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@ -357,7 +357,7 @@ static inline int vfp_double_type(vfp_double* s)
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// Unpack a double-precision float. Note that this returns the magnitude
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// Unpack a double-precision float. Note that this returns the magnitude
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// of the double-precision float mantissa with the 1. if necessary,
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// of the double-precision float mantissa with the 1. if necessary,
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// aligned to bit 62.
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// aligned to bit 62.
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static inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
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inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
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{
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{
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s->sign = vfp_double_packed_sign(val) >> 48;
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s->sign = vfp_double_packed_sign(val) >> 48;
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s->exponent = vfp_double_packed_exponent(val);
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s->exponent = vfp_double_packed_exponent(val);
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@ -379,7 +379,7 @@ static inline void vfp_double_unpack(vfp_double* s, s64 val, u32* fpscr)
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// Re-pack a double-precision float. This assumes that the float is
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// Re-pack a double-precision float. This assumes that the float is
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// already normalised such that the MSB is bit 30, _not_ bit 31.
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// already normalised such that the MSB is bit 30, _not_ bit 31.
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static inline s64 vfp_double_pack(vfp_double* s)
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inline s64 vfp_double_pack(const vfp_double* s)
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{
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{
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u64 val = ((u64)s->sign << 48) +
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u64 val = ((u64)s->sign << 48) +
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((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
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((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
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@ -415,7 +415,7 @@ struct op {
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u32 flags;
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u32 flags;
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};
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};
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static inline u32 fls(u32 x)
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inline u32 fls(u32 x)
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{
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{
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int r = 32;
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int r = 32;
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