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Merge pull request #652 from Subv/fadd32i
GPU: Implement the FADD32I shader instruction.
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commit
274d1fb0fc
@ -297,6 +297,13 @@ union Instruction {
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BitField<56, 1, u64> negate_a;
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} iadd32i;
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union {
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BitField<53, 1, u64> negate_b;
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BitField<54, 1, u64> abs_a;
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BitField<56, 1, u64> negate_a;
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BitField<57, 1, u64> abs_b;
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} fadd32i;
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union {
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BitField<20, 8, u64> shift_position;
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BitField<28, 8, u64> shift_length;
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@ -487,6 +494,7 @@ public:
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FADD_C,
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FADD_R,
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FADD_IMM,
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FADD32I,
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FMUL_C,
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FMUL_R,
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FMUL_IMM,
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@ -686,6 +694,7 @@ private:
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INST("0100110001011---", Id::FADD_C, Type::Arithmetic, "FADD_C"),
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INST("0101110001011---", Id::FADD_R, Type::Arithmetic, "FADD_R"),
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INST("0011100-01011---", Id::FADD_IMM, Type::Arithmetic, "FADD_IMM"),
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INST("000010----------", Id::FADD32I, Type::ArithmeticImmediate, "FADD32I"),
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INST("0100110001101---", Id::FMUL_C, Type::Arithmetic, "FMUL_C"),
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INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
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INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
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@ -968,6 +968,29 @@ private:
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regs.GetRegisterAsFloat(instr.gpr8) + " * " + GetImmediate32(instr), 1, 1);
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break;
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}
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case OpCode::Id::FADD32I: {
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std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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std::string op_b = GetImmediate32(instr);
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if (instr.fadd32i.abs_a) {
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op_a = "abs(" + op_a + ')';
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}
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if (instr.fadd32i.negate_a) {
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op_a = "-(" + op_a + ')';
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}
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if (instr.fadd32i.abs_b) {
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op_b = "abs(" + op_b + ')';
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}
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if (instr.fadd32i.negate_b) {
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op_b = "-(" + op_b + ')';
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}
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1);
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break;
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}
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}
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break;
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}
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