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Merge pull request #1115 from Subv/texs_mask
Shaders/TEXS: Write to the correct output register when swizzling.
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commit
296e57fa0e
@ -840,29 +840,29 @@ private:
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++shader.scope;
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shader.AddLine(coord);
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// TEXS has two destination registers. RG goes into gpr0+0 and gpr0+1, and BA
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// goes into gpr28+0 and gpr28+1
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size_t texs_offset{};
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// TEXS has two destination registers and a swizzle. The first two elements in the swizzle
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// go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1
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size_t src_elem{};
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for (const auto& dest : {instr.gpr0.Value(), instr.gpr28.Value()}) {
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size_t dest_elem{};
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for (unsigned elem = 0; elem < 2; ++elem) {
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if (!instr.texs.IsComponentEnabled(src_elem++)) {
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// Skip disabled components
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continue;
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}
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regs.SetRegisterToFloat(dest, elem + texs_offset, texture, 1, 4, false,
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dest_elem++);
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size_t written_components = 0;
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for (u32 component = 0; component < 4; ++component) {
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if (!instr.texs.IsComponentEnabled(component)) {
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continue;
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}
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if (!instr.texs.HasTwoDestinations()) {
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// Skip the second destination
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break;
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if (written_components < 2) {
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// Write the first two swizzle components to gpr0 and gpr0+1
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regs.SetRegisterToFloat(instr.gpr0, component, texture, 1, 4, false,
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written_components % 2);
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} else {
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ASSERT(instr.texs.HasTwoDestinations());
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// Write the rest of the swizzle components to gpr28 and gpr28+1
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regs.SetRegisterToFloat(instr.gpr28, component, texture, 1, 4, false,
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written_components % 2);
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}
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texs_offset += 2;
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++written_components;
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}
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--shader.scope;
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shader.AddLine('}');
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}
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